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1.发明公开公开(公告)号：US20230327679A1
公开(公告)日：2023-10-12
申请号：US17717061
申请日：2022-04-09
发明人： Chi Fung LOK
IPC分类号： H03M1/06
CPC分类号： H03M1/0607
摘要： A multi-stage pipelined Analog-to-Digital Converter (ADC) has an offset correction circuit embedded in the residue amplifier between stages. The offset corrector has a low-pass filter that filters the output of the residue amplifier, and the filtered offset is amplified and stored on an offset capacitor during an autozeroing phase of the residue amplifier. During an amplify phase of the residue amplifier, switches disconnect the amplifier from the offset capacitor and instead ground the input of the offset capacitor, and other switches connect the output terminal of the offset capacitor to the input of the residue amplifier. The offset stored on the offset capacitor is combined with the residue voltage from the first ADC stage's capacitor array and applied to an input of the residue amplifier to effectively subtract the detected offset. Two offset capacitors and sets of switches can be used to implement a differential offset corrector.
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公开(公告)号：US11146282B1
公开(公告)日：2021-10-12
申请号：US17140683
申请日：2021-01-04
发明人： Chi Fung Lok , Xiaoyong He , Zhi Jun Li
摘要： A first calibration measures capacitor array mis-match and updates a Look-Up Table (LUT) with calibrated weights that are copied to both a positive LUT and a negative LUT, and then adjusted for non-linearity errors by a second calibration using a Least Mean-Square (LMS) method. The binary code in the Successive-Approximation Register (SAR) is complemented to generate a complement code with a sign bit. When the sign bit is positive, entries for complement code bits=1 are read from the positive LUT and summed, a first offset added, and the sum normalized to get a corrected code. When the sign bit is negative, entries for complement code bits=0 are read from the negative LUT and summed, a second offset added, and the sum normalized to get the corrected code. A Multi-Variable Stochastic Gradient Descent method generates polynomial coefficients that further correct the corrected code.
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公开(公告)号：US11757459B2
公开(公告)日：2023-09-12
申请号：US17673947
申请日：2022-02-17
发明人： Chi Fung Lok
CPC分类号： H03M1/002 , H03M1/0604
摘要： A reference buffer has many legs each with an upper transistor, a lower transistor, and a resistor or current source as a tail device in series. The source or emitter of the upper (lower) transistor generates an upper (lower) reference voltage. This source follower transistor configuration has a low output impedance and high current. The gate or base of the upper (lower) transistors are driven by a first (second) control node. A control leg has an upper transistor, a lower transistor, and a tail device in series. The source and gate, or emitter and base, are connected together for the upper and lower transistors and generate the upper and lower control nodes. Alternately, the gate or base of the upper (lower) transistor is driven by an op amp receiving an upper (lower) bandgap voltage and the upper (lower) control node as negative feedback.
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公开(公告)号：US11641210B1
公开(公告)日：2023-05-02
申请号：US17537460
申请日：2021-11-29
发明人： Chi Fung Lok , Zhi Jun Li
摘要： An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. In each channel the ADC output is filtered, and a product derivative correlator generates a product derivative factor for correlation to two adjacent ADC channels. A matrix processor arranges the product derivative factors from the product derivative correlators into a matrix that is multiplied by a correlation matrix. The correlation matrix is a constant generated from an N×N shift matrix. The matrix processor outputs a sign-bit vector. Each bit in the sign-bit vector determines when tested SAR bits are set or cleared to adjust a channel's variable delay. Sampling clock and component timing skews are reduced to one LSB among all N channels.
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公开(公告)号：US11855651B2
公开(公告)日：2023-12-26
申请号：US17717061
申请日：2022-04-09
发明人： Chi Fung Lok
CPC分类号： H03M1/0607
摘要： A multi-stage pipelined Analog-to-Digital Converter (ADC) has an offset correction circuit embedded in the residue amplifier between stages. The offset corrector has a low-pass filter that filters the output of the residue amplifier, and the filtered offset is amplified and stored on an offset capacitor during an autozeroing phase of the residue amplifier. During an amplify phase of the residue amplifier, switches disconnect the amplifier from the offset capacitor and instead ground the input of the offset capacitor, and other switches connect the output terminal of the offset capacitor to the input of the residue amplifier. The offset stored on the offset capacitor is combined with the residue voltage from the first ADC stage's capacitor array and applied to an input of the residue amplifier to effectively subtract the detected offset. Two offset capacitors and sets of switches can be used to implement a differential offset corrector.
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公开(公告)号：US11750160B1
公开(公告)日：2023-09-05
申请号：US17717063
申请日：2022-04-09
发明人： Chi Fung Lok
IPC分类号： H03F3/45
CPC分类号： H03F3/45125 , H03F3/45197 , H03F3/45488
摘要： A differential residue amplifier fits between Analog-to-Digital Converter (ADC) stages. Switched-Capacitor Common-Mode Feedback circuits determine voltage shifts. An AC-coupled input network uses switched capacitors to shift upward voltages of the differential inputs to the residue amplifier to apply to an upper pair of p-channel differential transistors with sources connected to the power supply. The AC-coupled input network also shifts downward in voltage the differential inputs to the residue amplifier to apply to a lower pair of n-channel differential transistors with grounded sources. The drains of the p-channel differential transistors connect to differential outputs through p-channel cascode transistors. N-channel cascode transistors connect the drains of the n-channel differential transistors to the differential outputs. The drains of differential transistors can be input to differential amplifiers to drive the gates of the cascode transistors for gain boosting. No tail current is used, allowing for wider output-voltage swings with low supply voltages.
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公开(公告)号：US20230155598A1
公开(公告)日：2023-05-18
申请号：US17537460
申请日：2021-11-29
发明人： Chi Fung LOK , Zhi Jun LI
IPC分类号： H03M1/10
CPC分类号： H03M1/1014
摘要： An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. In each channel the ADC output is filtered, and a product derivative correlator generates a product derivative factor for correlation to two adjacent ADC channels. A matrix processor arranges the product derivative factors from the product derivative correlators into a matrix that is multiplied by a correlation matrix. The correlation matrix is a constant generated from an N×N shift matrix. The matrix processor outputs a sign-bit vector. Each bit in the sign-bit vector determines when tested SAR bits are set or cleared to adjust a channel's variable delay. Sampling clock and component timing skews are reduced to one LSB among all N channels.
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公开(公告)号：US20230261661A1
公开(公告)日：2023-08-17
申请号：US17673947
申请日：2022-02-17
发明人： Chi Fung LOK
CPC分类号： H03M1/002 , H03M1/0604
摘要： A reference buffer has many legs each with an upper transistor, a lower transistor, and a resistor or current source as a tail device in series. The source or emitter of the upper (lower) transistor generates an upper (lower) reference voltage. This source follower transistor configuration has a low output impedance and high current. The gate or base of the upper (lower) transistors are driven by a first (second) control node. A control leg has an upper transistor, a lower transistor, and a tail device in series. The source and gate, or emitter and base, are connected together for the upper and lower transistors and generate the upper and lower control nodes. Alternately, the gate or base of the upper (lower) transistor is driven by an op amp receiving an upper (lower) bandgap voltage and the upper (lower) control node as negative feedback.
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公开(公告)号：US20230155599A1
公开(公告)日：2023-05-18
申请号：US17580805
申请日：2022-01-21
发明人： Chi Fung LOK
CPC分类号： H03M1/1057 , H03M1/1215
摘要： An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. Each channel receives a sampling clock with a different phase delay. The sampling clocks are overlapping multi-phase clocks rather than non-overlapping. Overlapping the multi-phase clocks allows the sampling pulse width to be enlarged, providing more time for the sampling switch to remain open and allow analog voltages to equalize through the sampling switch. Higher sampling-clock frequencies are possible than when non-overlapping clocks are used. The sampling clock is boosted in voltage by a bootstrap driver to increase the gate voltage on the sampling switch, reducing the ON resistance. Sampling clock and component timing skews are reduced to one LSB among all N channels.
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公开(公告)号：US11646747B1
公开(公告)日：2023-05-09
申请号：US17580805
申请日：2022-01-21
发明人： Chi Fung Lok
CPC分类号： H03M1/1057 , H03M1/1215 , H03M1/0624 , H03M1/1014 , H03M1/1023 , H03M1/12 , H03M1/38
摘要： An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. Each channel receives a sampling clock with a different phase delay. The sampling clocks are overlapping multi-phase clocks rather than non-overlapping. Overlapping the multi-phase clocks allows the sampling pulse width to be enlarged, providing more time for the sampling switch to remain open and allow analog voltages to equalize through the sampling switch. Higher sampling-clock frequencies are possible than when non-overlapping clocks are used. The sampling clock is boosted in voltage by a bootstrap driver to increase the gate voltage on the sampling switch, reducing the ON resistance. Sampling clock and component timing skews are reduced to one LSB among all N channels.
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