公开(公告)号：US20070001716A1

公开(公告)日：2007-01-04

申请号：US11169862

申请日：2005-06-29

申请人： Hector Sanchez ,  Xinghai Tang ,  Carlos Greaves ,  Jim Nissen

发明人： Hector Sanchez ,  Xinghai Tang ,  Carlos Greaves ,  Jim Nissen

IPC分类号： H03B1/00

CPC分类号： H03K19/00315 ,  H03K19/018585

摘要： A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a state of the first preliminary drive signal AC coupled to the first signal, first and second drive circuits receiving the preliminary drive signals and providing first and second drive signals, where the first drive circuit operates within a second voltage range having a greater common mode voltage and where the second drive circuit operates within a third voltage range, and an output that switches an output node within a voltage range that is greater than a maximum voltage range. The first, second and third voltage ranges are each within the maximum voltage range suitable for thin-gate devices.

公开(公告)号：US20050276141A1

公开(公告)日：2005-12-15

申请号：US10854554

申请日：2004-05-26

申请人： Perry Pelley ,  Carlos Greaves

发明人： Perry Pelley ,  Carlos Greaves

IPC分类号： G11C7/00 ,  G11C11/406

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40615

摘要： A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

摘要翻译： 存储器（10）具有多个存储单元，用于接收低电压高频差分地址信号的串行地址端口（47）和用于接收高频低电压的串行输入/输出数据端口（52,54） 差分数据信号。 存储器（10）可以以两种不同模式之一工作，即正常模式和高速缓存行模式。 在高速缓存行模式下，内存可以从单个地址访问整个高速缓存行。 完全隐藏的刷新模式允许在高速缓存线模式下运行时进行及时的刷新操作。 数据通过在多个子阵列（15,17）中交错存储在存储器阵列（14）中。 在隐藏的刷新操作模式期间，一个子阵列（15）被访问，而另一个子阵列（17）被刷新。 两个或多个存储器（10）可以链接在一起以提供高速低功率存储器系统。

公开(公告)号：US20050111446A1

公开(公告)日：2005-05-26

申请号：US10721201

申请日：2003-11-25

申请人： Carlos Greaves ,  Harold Martin ,  Thang Nguyen ,  Jose Nunez

发明人： Carlos Greaves ,  Harold Martin ,  Thang Nguyen ,  Jose Nunez

IPC分类号： H04L12/413 ,  H04L12/56 ,  H04L12/28

CPC分类号： H04L49/351 ,  H04L49/201 ,  H04L49/3018

摘要： Hashing and pattern matching are used in an information processing system to process incoming messages from a network such as an Ethernet-based network. Using hashing and pattern matching increases the efficiency of message acceptance and rejection without increasing software-based processor tasks. A hash function and a pattern matching function are performed on a message received by an information processing system, and the message is selectively accepted based on at least one of a hash result and a pattern matching result. The incoming message can be searched for the existence of patterns and the absence of the patterns. The incoming message can be searched for the existence of multiple patterns. The results of pattern matching can be used not only for acceptance and rejection of messages, but also for other post-receipt tasks such as selective storage of incoming messages according to identified relative priorities or absolute criticality of messages having particular pattern matches.

摘要翻译： 在信息处理系统中使用散列和模式匹配来处理来自诸如以太网的网络之类的网络的传入消息。 使用散列和模式匹配增加了消息接受和拒绝的效率，而不增加基于软件的处理器任务。 对由信息处理系统接收到的消息执行散列函数和模式匹配功能，并且基于散列结果和模式匹配结果中的至少一个选择性地接受该消息。 可以搜索传入的消息中的模式的存在和模式的缺失。 可以搜索输入的消息以存在多个模式。 模式匹配的结果不仅可以用于消息的接受和拒绝，而且可以用于其他后接收任务，例如根据所识别的相对优先级或具有特定模式匹配的消息的绝对关键性选择性地存储传入消息。

公开(公告)号：US20070211554A1

公开(公告)日：2007-09-13

申请号：US11736231

申请日：2007-04-17

申请人： Perry Pelly ,  Carlos Greaves

发明人： Perry Pelly ,  Carlos Greaves

IPC分类号： G11C8/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40615

摘要： A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

摘要翻译： 存储器（10）具有多个存储单元，用于接收低电压高频差分地址信号的串行地址端口（47）和用于接收高频低电压的串行输入/输出数据端口（52,54） 差分数据信号。 存储器（10）可以以两种不同模式之一工作，即正常模式和高速缓存行模式。 在高速缓存行模式下，内存可以从单个地址访问整个高速缓存行。 完全隐藏的刷新模式允许在高速缓存线模式下运行时进行及时的刷新操作。 数据通过在多个子阵列（15,17）中交错存储在存储器阵列（14）中。 在隐藏的刷新操作模式期间，一个子阵列（15）被访问，而另一个子阵列（17）被刷新。 两个或多个存储器（10）可以链接在一起以提供高速低功率存储器系统。

公开(公告)号：US20050108943A1

公开(公告)日：2005-05-26

申请号：US10721196

申请日：2003-11-25

申请人： Harold Martin ,  Carlos Greaves ,  Thang Nguyen ,  Jose Nunez

发明人： Harold Martin ,  Carlos Greaves ,  Thang Nguyen ,  Jose Nunez

IPC分类号： E05F15/20 ,  G01C17/38 ,  G01P21/00 ,  G01R31/08 ,  G06F19/00 ,  H04L20060101 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04L47/10 ,  H04L45/745 ,  H04L47/2441

摘要： Hashing and pattern matching are used in an information processing system to process incoming messages from a network such as an Ethernet-based network. Using hashing and pattern matching increases the efficiency of message acceptance and rejection without increasing software-based processor tasks. A hash function and a pattern matching function are performed on a message received by an information processing system, and the message is selectively accepted based on at least one of a hash result and a pattern matching result. The incoming message can be searched for the existence of patterns and the absence of the patterns. The incoming message can be searched for the existence of multiple patterns. The results of pattern matching can be used not only for acceptance and rejection of messages, but also for other post-receipt tasks such as selective storage of incoming messages according to identified relative priorities or absolute criticality of messages having particular pattern matches.

摘要翻译： 在信息处理系统中使用散列和模式匹配来处理来自诸如以太网的网络之类的网络的传入消息。 使用散列和模式匹配增加了消息接受和拒绝的效率，而不增加基于软件的处理器任务。 对由信息处理系统接收到的消息执行散列函数和模式匹配功能，并且基于散列结果和模式匹配结果中的至少一个选择性地接受该消息。 可以搜索传入的消息中的模式的存在和模式的缺失。 可以搜索输入的消息以存在多个模式。 模式匹配的结果不仅可以用于消息的接收和拒绝，而且可以用于其他后接收任务，例如根据所识别的相对优先级或具有特定模式匹配的消息的绝对关键性选择性地存储传入消息。

公开(公告)号：US20070008001A1

公开(公告)日：2007-01-11

申请号：US11170398

申请日：2005-06-29

申请人： Hector Sanchez ,  Carlos Greaves ,  Jim Nissen ,  Xinghai Tang

发明人： Hector Sanchez ,  Carlos Greaves ,  Jim Nissen ,  Xinghai Tang

IPC分类号： H03K19/0175

CPC分类号： H03K3/356113

摘要： A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to opposite states within a second voltage range between third and fourth supply voltages in response to switching of the first and second nodes. The protection layer couples the first and second nodes to third and fourth nodes via respective first and second isolation paths. The isolation paths operate to keep the first and second nodes within the first voltage range and to keep the third and fourth nodes within the second voltage range. Isolation enables the use of thin gate-oxide devices for speed while extending the voltage range beyond the maximum voltage allowable for a single thin gate-oxide device.

公开(公告)号：US20060197608A1

公开(公告)日：2006-09-07

申请号：US11069664

申请日：2005-03-01

申请人： Hector Sanchez ,  Carlos Greaves ,  Jim Nissen ,  Xinghai Tang

发明人： Hector Sanchez ,  Carlos Greaves ,  Jim Nissen ,  Xinghai Tang

IPC分类号： H03L7/00

CPC分类号： H03L7/0995 ,  H03K3/0377 ,  H03K5/084 ,  H03K5/133 ,  H03K2005/00071 ,  H03L7/0896

摘要： A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.