公开(公告)号：US09659922B2

公开(公告)日：2017-05-23

申请号：US13917580

申请日：2013-06-13

申请人： Rouying Zhan ,  Chai Ean Gill

发明人： Rouying Zhan ,  Chai Ean Gill

IPC分类号： H01L27/02

CPC分类号： H01L27/0262 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66234 ,  H02H9/046

摘要： An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.

公开(公告)号：US09583603B2

公开(公告)日：2017-02-28

申请号：US13764523

申请日：2013-02-11

申请人： Rouying Zhan ,  Chai Ean Gill ,  William G. Cowden ,  Changsoo Hong

发明人： Rouying Zhan ,  Chai Ean Gill ,  William G. Cowden ,  Changsoo Hong

IPC分类号： H01L29/73 ,  H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L29/735 ,  H01L29/06

CPC分类号： H01L29/73 ,  H01L27/0277 ,  H01L29/0653 ,  H01L29/66325 ,  H01L29/735 ,  H01L29/7835

摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a base region in the semiconductor substrate and having a first conductivity type, an emitter region in the base region and having a second conductivity type, a collector region in the semiconductor substrate, spaced from the base region, and having the second conductivity type, a breakdown trigger region having the second conductivity type, disposed laterally between the base region and the collector region to define a junction across which breakdown occurs to trigger the ESD protection device to shunt ESD discharge current, and a gate structure supported by the semiconductor substrate over the breakdown trigger region and electrically tied to the base region and the emitter region. The lateral width of the breakdown trigger region is configured to establish a voltage level at which the breakdown occurs.

摘要翻译： 静电放电（ESD）保护装置包括半导体衬底，半导体衬底中的基极区域，具有第一导电类型，基极区域中的发射极区域，具有第二导电类型，半导体衬底中的集电极区域间隔开 具有第二导电类型的具有第二导电类型的击穿触发区域横向设置在基极区域和集电极区域之间以限定发生击穿的结，以触发ESD保护装置以分流ESD放电 电流以及由击穿触发区域上的半导体衬底支撑并电连接到基极区域和发射极区域的栅极结构。 击穿触发区域的横向宽度被配置为建立发生击穿的电压电平。

公开(公告)号：US20160013177A1

公开(公告)日：2016-01-14

申请号：US14327191

申请日：2014-07-09

申请人： ROUYING ZHAN ,  CHAI EAN GILL

发明人： ROUYING ZHAN ,  CHAI EAN GILL

IPC分类号： H01L27/02 ,  H01L27/12 ,  H01L21/265 ,  H01L29/06 ,  H01L21/8222 ,  H01L21/84 ,  H01L29/08

CPC分类号： H01L27/0259 ,  H01L21/26513 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/732

摘要： ESD protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base well region having a first conductivity type, a collector region of the opposite conductivity type, and a second base well region having a dopant concentration greater than the first base well region, and a portion of the second base well region is disposed between the first base well region and the collector region. A third base well region with a different dopant concentration is disposed between the collector region and the second base well region. At least a portion of the first base well region is disposed between a base contact region and an emitter region within the second base well region.

摘要翻译： 提供ESD保护器件结构及相关制造方法。 示例性的半导体保护装置包括具有第一导电类型的第一基极阱区域，具有相反导电类型的集电极区域和具有大于第一基极阱区域的掺杂剂浓度的第二基极阱区域，以及第二基极阱区域的一部分 基极区域设置在第一基极阱区域和集电极区域之间。 具有不同掺杂浓度的第三基极阱区域设置在集电极区域和第二基极阱区域之间。 第一基极阱区域的至少一部分设置在第二基极阱区域内的基极接触区域和发射极区域之间。

公开(公告)号：US09112351B2

公开(公告)日：2015-08-18

申请号：US13759241

申请日：2013-02-05

申请人： Wen-Yi Chen ,  Chai Ean Gill

发明人： Wen-Yi Chen ,  Chai Ean Gill

IPC分类号： H02H9/04 ,  H01L27/02

CPC分类号： H02H9/046 ,  H01L27/0285

摘要： An integrated circuit is provided. The integrated circuit may include, but is not limited to, a first node, a second node configured to be coupled to ground, an output driver, and a electrostatic discharge circuit electrically coupled to the first node, the second node, and the output driver. The electrostatic discharge circuit may include, but is not limited a high-pass filter configured to detect an electrostatic discharge event at the first node, a driving stage circuit electrically coupled to the high-pass filter and the output driver, the driving stage circuit configured to receive a signal from the high-pass filter when the high-pass filter detects the electrostatic discharge event and further configured to shunt an input of the output driver to the second node in response to the signal from the high-pass filter, and a step-down circuit electrically coupled to the driving stage circuit and configured to bias the driving stage circuit.

摘要翻译： 提供集成电路。 集成电路可以包括但不限于第一节点，被配置为耦合到地的第二节点，输出驱动器和电耦合到第一节点，第二节点和输出驱动器的静电放电电路 。 静电放电电路可以包括但不限于被配置为检测第一节点处的静电放电事件的高通滤波器，电耦合到高通滤波器和输出驱动器的驱动级电路，驱动级电路配置 当所述高通滤波器检测到所述静电放电事件时，接收来自所述高通滤波器的信号，并且还被配置为响应于来自所述高通滤波器的信号将所述输出驱动器的输入分流到所述第二节点，并且 降压电路电耦合到驱动级电路并且被配置为偏置驱动级电路。

公开(公告)号：US20140367830A1

公开(公告)日：2014-12-18

申请号：US13917580

申请日：2013-06-13

申请人： Rouying Zhan ,  Chai Ean Gill

发明人： Rouying Zhan ,  Chai Ean Gill

IPC分类号： H01L27/02 ,  H01L21/8222 ,  H01L27/082

CPC分类号： H01L27/0262 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66234 ,  H02H9/046

摘要： An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.

摘要翻译： 静电放电保护夹具包括衬底和衬底上的第一静电放电保护器件。 第一静电放电保护器件包括衬底上的掩埋层。 掩埋层具有具有第一掺杂浓度的第一区域和具有第二掺杂浓度的第二区域。 第一掺杂浓度大于第二掺杂浓度。 第一静电放电保护器件包括在掩埋层上的第一晶体管。 第一晶体管具有耦合到静电放电保护钳的第一阴极端子的发射极。 第一静电放电保护器件包括在掩埋层上的第二晶体管。 第二晶体管具有耦合到静电放电保护夹的第一阳极端子的发射极。 第一晶体管的集电极和第二晶体管的集电极在掩埋层的第一区域之上。

公开(公告)号：US08647955B2

公开(公告)日：2014-02-11

申请号：US13770548

申请日：2013-02-19

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L21/8222 ,  H01L23/62

CPC分类号： H01L21/8228 ,  H01L27/0259 ,  H01L29/66234

摘要： Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1

摘要翻译： 提供了形成静电放电保护（ESD）夹具的方法。 在一个实施例中，该方法包括形成至少一个具有延伸到衬底中的第一导电类型的第一阱区的晶体管。 至少一个晶体管形成有具有第二相反导电类型的另一阱区，其延伸到衬底中以部分地形成集电极。 晶体管阱区的横向边缘被隔开距离D，距离D至少部分地确定ESD钳位的阈值电压Vt1。 第一导电类型的基极接触形成在第一阱区中，并且与第二导电类型的发射极分开横向距离Lbe。 选择第一掺杂浓度和横向距离Lbe以在1

公开(公告)号：US20100320501A1

公开(公告)日：2010-12-23

申请号：US12487031

申请日：2009-06-18

申请人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

IPC分类号： H01L29/73 ,  H01L21/33

CPC分类号： H01L21/00 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/66121 ,  H01L29/87

摘要： An electrostatic discharge (ESD) protection device (11, 60, 80) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24), comprises, first (70, 90) and second (72, 92) merged bipolar transistors (70, 90; 72, 92). A base (62, 82) of the first (70, 90) transistor serves as collector of the second transistor (72, 92) and the base of the second transistor (72, 92) serves as collector of the first (70, 90) transistor, the bases (62, 82) having, respectively, first width (74, 94) and second width (76, 96). A first resistance (78, 98) is coupled between an emitter (67, 87) and base (62, 82) of the first transistor (70, 90) and a second resistance (79, 99) is coupled between an emitter (68, 88) and base (64, 42) of the second transistor (92, 92). ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths (74, 94; 76, 96) and resistances (78, 98; 79, 99). By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage).

摘要翻译： 耦合在核心电路（24）的输入输出（I / O）（22）和公共（23）端子之间的静电放电（ESD）保护装置（11,60,80）包括：第一（70,90） 和第二（72,92）合并的双极晶体管（70,90; 72,92）。 第一（70,90）晶体管的基极（62,82）用作第二晶体管（72,92）的集电极，第二晶体管（72,92）的基极用作第一晶体管（70,90）的集电极 ）晶体管，所述基座（62,82）分别具有第一宽度（74,94）和第二宽度（76,96）。 第一电阻（78,98）耦合在第一晶体管（70,90）的发射极（67,87）和基极（62,82）之间，第二电阻（79,99）耦合在发射极（68,98） ，88）和第二晶体管（92,92）的基极（64,42）。 可以通过选择合适的基准宽度（74,94,76,96）和电阻（78,98,79,99）来独立地优化ESD触发电压Vt1和保持电压Vh。 通过将Vh增加到大致相等的Vt1，ESD保护更加坚固，特别是对于具有窄设计窗口的应用，例如，工作电压接近劣化电压）。

公开(公告)号：US07723823B2

公开(公告)日：2010-05-25

申请号：US12178800

申请日：2008-07-24

申请人： Chai Ean Gill ,  Changsoo Hong ,  James D. Whitfield ,  Rouying Zhan

发明人： Chai Ean Gill ,  Changsoo Hong ,  James D. Whitfield ,  Rouying Zhan

IPC分类号： H01L23/62

CPC分类号： H01L27/0259 ,  H01L29/735 ,  H01L29/861

摘要： An improved lateral bipolar electrostatic discharge (ESD) protection device (40) comprises a semiconductor (SC) substrate (42), an overlying epitaxial SC layer (44), emitter-collector regions (48, 50) laterally spaced apart by a first distance (52) in the SC layer, a base region (54) adjacent the emitter region (48) extending laterally toward and separated from the collector region (50) by a base-collector spacing (56) that is selected to set the desired trigger voltage Vt1. By providing a buried layer region (49) under the emitter region (48) Ohmically coupled thereto, but not providing a comparable buried layer region (51) under the collector region (50), an asymmetrical structure is obtained in which the DC trigger voltage (Vt1DC) and transient trigger voltage (Vt1TR) are closely matched so that |Vt1TR−Vt1DC|˜0. This close matching increases the design margin and provides a higher performance ESD device (40) that is less sensitive to process variations, thereby improving manufacturing yield and reducing cost.

摘要翻译： 改进的侧向双极性静电放电（ESD）保护装置（40）包括半导体（SC）衬底（42），上覆外延SC层（44），发射极 - 集电区域（48,50），横向间隔开第一距离 （52），邻近所述发射极区域（48）的基极区域（54），所述基极区域（54）通过基极 - 集电极间隔（56）侧向朝向并且与所述集电极区域（50）分离，所述基极集电极间隔（56）被选择以设定所述期望的触发 电压Vt1。 通过在发射极区域（48）的下方设置一个掩埋层区域（49），所述掩埋层区域（49）与其集电极区域（50）的欧姆耦合，但不提供可比较的掩埋层区域（51），获得非对称结构，其中直流触发电压 （Vt1DC）和瞬态触发电压（Vt1TR）紧密匹配，使得| Vt1TR-Vt1DC | ~0。 这种紧密匹配增加了设计裕度，并提供了对工艺变化不那么敏感的更高性能的ESD器件（40），从而提高了制造产量并降低了成本。

公开(公告)号：US20090273867A1

公开(公告)日：2009-11-05

申请号：US12112209

申请日：2008-04-30

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/04

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35′) with gates (38, 38′) coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT (25) during normal operation is much reduced.

摘要翻译： 被保护半导体SC器件的输入输出（I / O）（22）和公共（GND）（23）端子耦合的静电放电（ESD）钳位（41,41,61,71,81,91） IC（24）包括耦合在GND（23）和I / O（22）之间的源极 - 漏极（26,27）的ESD晶体管（ESDT）（25），耦合在栅极 28）和源极（26）和耦合在ESDT体（29）和源极（26）之间的第二电阻器（30）。 并联电阻器（30,32）是与一个或多个偏置电源Vb，Vb'耦合的门（38,38'）的控制晶体管（35,35'）。 设备或IC（24）的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。 在正常运行期间通过ESDT（25）的寄生泄漏大大减少。

公开(公告)号：US09786652B2

公开(公告)日：2017-10-10

申请号：US14854366

申请日：2015-09-15

申请人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

IPC分类号： H01L29/74 ,  H01L29/747 ,  H01L29/00 ,  H01L21/331 ,  H01L27/082 ,  H01L29/73 ,  H01L27/02 ,  H01L29/66 ,  H01L23/60 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L27/0259 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/082 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/73 ,  H01L29/7317 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.