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1.发明申请公开(公告)号：US20110119560A1
公开(公告)日：2011-05-19
申请号：US13012955
申请日：2011-01-25
申请人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
发明人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
CPC分类号： G06F11/1072 , G06F11/1068 , G06F12/0238 , G06F13/1668 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/35 , H03M13/3715
摘要： An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.
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2.发明授权Flash memory device error correction code controllers and related methods and memory systems 有权闪存设备纠错码控制器及相关方法和存储系统公开(公告)号：US07904790B2
公开(公告)日：2011-03-08
申请号：US11692992
申请日：2007-03-29
申请人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
发明人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
IPC分类号： G11C29/00
CPC分类号： G06F11/1072 , G06F11/1068 , G06F12/0238 , G06F13/1668 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/35 , H03M13/3715
摘要： An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.
摘要翻译： 用于存储M位数据（M：等于或大于2的正整数）的闪速存储器件的ECC控制器包括编码器和解码器。 编码器使用第一纠错方案生成要存储在闪速存储装置中的输入数据的第一ECC数据，并使用第二纠错方案为输入数据生成第二ECC数据。 输入数据，第一ECC数据和第二ECC数据被存储在闪存设备中。 解码器计算从闪速存储器件读取的数据中的错误数目，并且可以使用第一ECC数据和第二ECC数据中的一个选择性地基于错误数来校正读取数据中的错误。
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3.发明申请公开(公告)号：US20090316485A1
公开(公告)日：2009-12-24
申请号：US12487381
申请日：2009-06-18
申请人： Seok-Won Heo , Min-Soo Kang , Chang-Duck Lee , Soong-Man Shin
发明人： Seok-Won Heo , Min-Soo Kang , Chang-Duck Lee , Soong-Man Shin
CPC分类号： G11C16/10 , G11C7/16 , G11C11/5628
摘要： A memory card including a memory controller, a memory system and a method to control a memory are provided. The memory card includes a flash memory, a memory interface outputting a writing data signal to be written into the flash memory, and a multi-level converter transforming the writing data signal into a writing voltage signal to be provided to the flash memory. The writing voltage signal has one of different voltage levels in accordance with plural bits of the writing data signal.
摘要翻译： 提供了包括存储器控制器，存储器系统和控制存储器的方法的存储卡。 存储卡包括闪速存储器，输出要写入闪速存储器的写入数据信号的存储器接口，以及将写入数据信号转换成写入电压信号以提供给闪速存储器的多电平转换器。 写入电压信号根据写入数据信号的多个比特具有不同的电压电平之一。
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4.发明申请Apparatus and methods for controlling output of clock signal and systems including the same 有权用于控制时钟信号的输出的装置和方法及包括其的系统公开(公告)号：US20070124558A1
公开(公告)日：2007-05-31
申请号：US11418559
申请日：2006-05-05
申请人： Chang-Duck Lee , Sam-Yong Bahng , Sin-Ho Yang , Kui-Yon Mun
发明人： Chang-Duck Lee , Sam-Yong Bahng , Sin-Ho Yang , Kui-Yon Mun
IPC分类号： G06F13/00
CPC分类号： G06F13/4243 , G06F13/362 , Y02D10/14 , Y02D10/151
摘要： An apparatus for controlling data exchange with a memory device includes an interface configured to receive an arbitration signal indicating when the apparatus has use of a shared bus and an interface to the memory device configured to provide a clock signal to the memory device that synchronizes data exchange between the apparatus and the memory device. A selection circuit selectively supplies the clock signal to the memory device responsive to the arbitration signal
摘要翻译： 一种用于控制与存储器件的数据交换的设备包括：接口，被配置为接收指示何时该设备使用共享总线的仲裁信号;以及与该存储器件的接口，该接口被配置为向存储器件提供同步数据交换的时钟信号 在设备和存储设备之间。 选择电路响应于仲裁信号选择性地将时钟信号提供给存储器件
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5.发明申请FLASH MEMORY SYSTEM FOR IMPROVING READ PERFORMANCE AND READ METHOD THEREOF 审中-公开用于改进阅读性能的闪速存储器系统及其读取方法公开(公告)号：US20080222491A1
公开(公告)日：2008-09-11
申请号：US11694237
申请日：2007-03-30
申请人： Chang-Duck Lee , Seok-Won Heo , Si-Yung Park , Dong-Ryoul Lee
发明人： Chang-Duck Lee , Seok-Won Heo , Si-Yung Park , Dong-Ryoul Lee
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A method of transmitting data from a flash memory device to a host includes: detecting whether the data includes an error or not; performing an error correction operation for correcting the data having the error when the error exists in the data; and sequentially storing the data having the error and a plurality of subsequent read data without outputting. The storing of the data is performed during the performing of the error correction operation.
摘要翻译： 从闪速存储器装置向主机发送数据的方法包括：检测数据是否包含错误; 执行纠错操作，用于在数据中存在错误时校正具有错误的数据; 并且顺序地存储具有错误的数据和多个后续读取数据而不输出。 在执行纠错操作期间执行数据的存储。
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公开(公告)号：US20080175089A1
公开(公告)日：2008-07-24
申请号：US11695267
申请日：2007-04-02
申请人： Seok-Won Heo , Chang-Duck Lee , Jae-Sung Yu , Dong-Ryoul Lee
发明人： Seok-Won Heo , Chang-Duck Lee , Jae-Sung Yu , Dong-Ryoul Lee
IPC分类号： G11C8/12
CPC分类号： G06F13/1694
摘要： A flash memory card including a main memory core, a removable supplementary memory core, and a controller operating to control the main and supplementary memory cores. The supplementary memory core includes a plurality of memory cores and is replaceable.
摘要翻译： 一种闪存卡，包括主存储器核心，可移动辅助存储器核心和操作以控制主和辅助存储器核心的控制器。 辅助存储器核心包括多个存储器核心并且是可更换的。
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7.发明授权Flash memory device error correction code controllers and related methods and memory systems 有权闪存设备纠错码控制器及相关方法和存储系统公开(公告)号：US08788905B2
公开(公告)日：2014-07-22
申请号：US13012955
申请日：2011-01-25
申请人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
发明人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
CPC分类号： G06F11/1072 , G06F11/1068 , G06F12/0238 , G06F13/1668 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/35 , H03M13/3715
摘要： An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.
摘要翻译： 用于存储M位数据（M：等于或大于2的正整数）的闪速存储器件的ECC控制器包括编码器和解码器。 编码器使用第一纠错方案生成要存储在闪速存储装置中的输入数据的第一ECC数据，并使用第二纠错方案为输入数据生成第二ECC数据。 输入数据，第一ECC数据和第二ECC数据被存储在闪速存储器件中。 解码器计算从闪速存储器件读取的数据中的错误数目，并且可以使用第一ECC数据和第二ECC数据中的一个选择性地基于错误数来校正读取数据中的错误。
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8.发明授权Flash memory device error correction code controllers and related methods and memory systems 有权闪存设备纠错码控制器及相关方法和存储系统公开(公告)号：US08112692B2
公开(公告)日：2012-02-07
申请号：US13012984
申请日：2011-01-25
申请人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
发明人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
IPC分类号： G11C29/00
CPC分类号： G06F11/1072 , G06F11/1068 , G06F12/0238 , G06F13/1668 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/35 , H03M13/3715
摘要： An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.
摘要翻译： 用于存储M位数据（M：等于或大于2的正整数）的闪速存储器件的ECC控制器包括编码器和解码器。 编码器使用第一纠错方案生成要存储在闪速存储装置中的输入数据的第一ECC数据，并使用第二纠错方案为输入数据生成第二ECC数据。 输入数据，第一ECC数据和第二ECC数据被存储在闪存设备中。 解码器计算从闪速存储器件读取的数据中的错误数目，并且可以使用第一ECC数据和第二ECC数据中的一个选择性地基于错误数来校正读取数据中的错误。
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9.发明授权Apparatus and methods for controlling output of clock signal and systems including the same 有权用于控制时钟信号的输出的装置和方法及包括其的系统公开(公告)号：US07698524B2
公开(公告)日：2010-04-13
申请号：US11418559
申请日：2006-05-05
申请人： Chang-Duck Lee , Sam-Yong Bahng , Sin-Ho Yang , Kui-Yon Mun
发明人： Chang-Duck Lee , Sam-Yong Bahng , Sin-Ho Yang , Kui-Yon Mun
CPC分类号： G06F13/4243 , G06F13/362 , Y02D10/14 , Y02D10/151
摘要： An apparatus for controlling data exchange with a memory device includes an interface configured to receive an arbitration signal indicating when the apparatus has use of a shared bus and an interface to the memory device configured to provide a clock signal to the memory device that synchronizes data exchange between the apparatus and the memory device. A selection circuit selectively supplies the clock signal to the memory device responsive to the arbitration signal.
摘要翻译： 一种用于控制与存储器件的数据交换的设备包括：接口，被配置为接收指示何时该设备使用共享总线的仲裁信号;以及与该存储器件的接口，该接口被配置为向存储器件提供同步数据交换的时钟信号 在设备和存储设备之间。 选择电路响应于仲裁信号选择性地将时钟信号提供给存储器件。
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10.发明申请Apparatus and Methods for Controlling Memory Access Responsive to an ATA Transmission Parameter 审中-公开用于控制响应于ATA传输参数的存储器访问的装置和方法公开(公告)号：US20080140879A1
公开(公告)日：2008-06-12
申请号：US11951453
申请日：2007-12-06
申请人： Chang-Duck Lee , Kui-Yon Mun
发明人： Chang-Duck Lee , Kui-Yon Mun
IPC分类号： G06F13/28
摘要： A memory system includes a memory and a memory controller coupled to the memory and configured to be connected to an advanced technology attachment (ATA) host, the memory controller including a memory interface configured to access to the memory and configured to control an access cycle to the memory by the memory interface in accordance with date rate information for the ATA host. The data rate information may include an ATA transmission mode of the ATA host.
摘要翻译： 存储器系统包括存储器和存储器控制器，其耦合到存储器并且被配置为连接到高级技术附件（ATA）主机，存储器控制器包括被配置为访问存储器并被配置为控制访问周期的存储器接口 内存由内存接口按照ATA主机的日期速率信息。 数据速率信息可以包括ATA主机的ATA传输模式。
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