公开(公告)号：US07961057B2

公开(公告)日：2011-06-14

申请号：US12200009

申请日：2008-08-28

申请人： Beng Hwee Ong ,  Minjie Wu ,  Wee Liang Lien ,  Chang-Fu Kuo

发明人： Beng Hwee Ong ,  Minjie Wu ,  Wee Liang Lien ,  Chang-Fu Kuo

IPC分类号： H03B19/12

CPC分类号： H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

摘要： An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency.

摘要翻译： 提供集成电路和装置。 集成电路包括偏置电路，LC谐振电路和电流模式逻辑（CML）分频器。 偏置电路产生第一和第二偏置电压。 LC谐振器电路产生具有振荡频率的振荡信号。 耦合到偏置电路和LC谐振器电路的由第一和第二偏置电压偏置的CML分频器接收振荡信号以产生具有振荡频率的分数速率的输出频率的输出信号。 振荡信号包括AC和DC分量，CML分频器接收AC分量以确定注入频率，并重新使用DC分量来提供尾电流以确定CML分频器的固有频率。 输出频率由注入频率和固有频率决定。

公开(公告)号：US07679876B2

公开(公告)日：2010-03-16

申请号：US11687690

申请日：2007-03-19

申请人： Beng Hwee Ong ,  Wee Liang Lien ,  Min Jie Wu ,  Chang-Fu Kuo

发明人： Beng Hwee Ong ,  Wee Liang Lien ,  Min Jie Wu ,  Chang-Fu Kuo

IPC分类号： H02H9/08

CPC分类号： G05F1/573

摘要： A system capable of limiting a current through a load and a method thereof. The system comprises a current sensor, a determination circuit, and a current mirror circuit. The current sensor, coupled to the load, produces a current indication indicating the current. The determination circuit, coupled to the current sensor, generates a short-circuit signal when the current exceeds a predetermined threshold. The current mirror circuit, coupled to a voltage source, the current sensor and the determination circuit, comprises a current mirror and a bypass path, delivers a mirrored current from the current mirror to the load upon receiving the short-circuit signal, and passes the current from the voltage source through the bypass path to the load in the absence of the short-circuit signal.

摘要翻译： 能够限制通过负载的电流的系统及其方法。 该系统包括电流传感器，确定电路和电流镜电路。 耦合到负载的电流传感器产生指示电流的电流指示。 耦合到电流传感器的确定电路当电流超过预定阈值时产生短路信号。 耦合到电压源的电流镜电路，电流传感器和确定电路包括电流镜和旁路路径，在接收到短路信号时将来自电流镜的镜像电流传送到负载，并且通过 在不存在短路信号的情况下，电压从电源通过旁通路径到负载。

公开(公告)号：US20110116578A1

公开(公告)日：2011-05-19

申请号：US13013552

申请日：2011-01-25

申请人： Chang-Fu Kuo ,  Min Jie Wu ,  Beng Hwee Ong ,  Wee Liang Lien

发明人： Chang-Fu Kuo ,  Min Jie Wu ,  Beng Hwee Ong ,  Wee Liang Lien

IPC分类号： H03D3/24 ,  H04B1/10

CPC分类号： H04B1/28 ,  H04B1/3805

摘要： A receiver includes a mixer, a poly phase filter, a channel select filter, an analog-to-digital converter and a HI/LO side reject selection unit. The mixer downconverts a signal to generate an in-phase signal and a quadrature signal. The poly phase filter for generates differential IF signals based on the in-phase signal and the quadrature signal. The channel select filter filters out unwanted channel signals from the differential IF signals. The analog-to-digital converter converts the filtered signal into a digital output signal. The HI/LO side reject selection unit is coupled between the mixer and the poly phase filter and capable of rejecting image signals while the mixer is at a high side frequency or at a low side frequency.

摘要翻译： 接收机包括混频器，多相滤波器，通道选择滤波器，模数转换器和HI / LO侧拒绝选择单元。 混频器将信号下变频以产生同相信号和正交信号。 多相滤波器，用于基于同相信号和正交信号产生差分IF信号。 通道选择滤波器滤除差分IF信号中不需要的通道信号。 模数转换器将滤波后的信号转换为数字输出信号。 HI / LO侧拒绝选择单元耦合在混频器和多相滤波器之间，并且能够在混频器处于高侧频率或低频率时拒绝图像信号。

公开(公告)号：US07899137B2

公开(公告)日：2011-03-01

申请号：US11617962

申请日：2006-12-29

申请人： Chang-Fu Kuo ,  Min Jie Wu ,  Beng Hwee Ong ,  Wee Liang Lien

发明人： Chang-Fu Kuo ,  Min Jie Wu ,  Beng Hwee Ong ,  Wee Liang Lien

IPC分类号： H03D3/24 ,  H04L27/22

CPC分类号： H04B1/28 ,  H04B1/3805

摘要： A Global Positioning System (GPS) receiver integrated with a cellular phone system, comprising a single-balanced mixer, a poly phase filter, a channel select filter, an analog-to-digital converter, a reference frequency source, and a PLL unit is disclosed. The single-balanced mixer downconverts a GPS signal to generate an in-phase signal I and a quadrature signal Q. The poly phase filter generates an IF signal based on the in-phase signal I and the quadrature signal Q. The channel select filter receives the IF signal to filter unwanted channel signals. The analog-to-digital converter converts the signal from the channel select filter to a digital output signal. The reference frequency source provides a reference frequency to the analog-to-digital converter. The PLL unit receives the reference frequency for generating a clock signal to the single-balanced mixer for downconversion.

摘要翻译： 与蜂窝电话系统集成的全球定位系统（GPS）接收机，包括单平衡混频器，多相滤波器，信道选择滤波器，模数转换器，参考频率源和PLL单元。 披露 单平衡混频器将GPS信号下变频以产生同相信号I和正交信号Q.多相滤波器基于同相信号I和正交信号Q产生IF信号。频道选择滤波器接收 IF信号滤除不需要的信道信号。 模数转换器将来自通道选择滤波器的信号转换为数字输出信号。 参考频率源为模数转换器提供参考频率。 PLL单元接收用于产生用于下变频的单平衡混频器的时钟信号的参考频率。

公开(公告)号：US20080089445A1

公开(公告)日：2008-04-17

申请号：US11617962

申请日：2006-12-29

申请人： Chang-Fu Kuo ,  Min Jie Wu ,  Beng Hwee Ong ,  Wee Liang Lien

发明人： Chang-Fu Kuo ,  Min Jie Wu ,  Beng Hwee Ong ,  Wee Liang Lien

IPC分类号： H03D3/24 ,  H04B1/10

CPC分类号： H04B1/28 ,  H04B1/3805

摘要： A Global Positioning System (GPS) receiver integrated with a cellular phone system, comprising a single-balanced mixer, a poly phase filter, a channel select filter, an analog-to-digital converter, a reference frequency source, and a PLL unit is disclosed. The single-balanced mixer downconverts a GPS signal to generate an in-phase signal I and a quadrature signal Q. The poly phase filter generates an IF signal based on the in-phase signal I and the quadrature signal Q. The channel select filter receives the IF signal to filter unwanted channel signals. The analog-to-digital converter converts the signal from the channel select filter to a digital output signal. The reference frequency source provides a reference frequency to the analog-to-digital converter. The PLL unit receives the reference frequency for generating a clock signal to the single-balanced mixer for downconversion.

摘要翻译： 与蜂窝电话系统集成的全球定位系统（GPS）接收机，包括单平衡混频器，多相滤波器，信道选择滤波器，模数转换器，参考频率源和PLL单元。 披露 单平衡混频器将GPS信号下变频以产生同相信号I和正交信号Q.多相滤波器基于同相信号I和正交信号Q产生IF信号。频道选择滤波器接收 IF信号滤除不需要的信道信号。 模数转换器将来自通道选择滤波器的信号转换为数字输出信号。 参考频率源为模数转换器提供参考频率。 PLL单元接收用于产生用于下变频的单平衡混频器的时钟信号的参考频率。

公开(公告)号：US20070268643A1

公开(公告)日：2007-11-22

申请号：US11687690

申请日：2007-03-19

申请人： Beng Hwee Ong ,  Wee Liang Lien ,  Min Jie Wu ,  Chang-Fu Kuo

发明人： Beng Hwee Ong ,  Wee Liang Lien ,  Min Jie Wu ,  Chang-Fu Kuo

IPC分类号： H02H9/08

CPC分类号： G05F1/573

摘要： A system capable of limiting a current through a load and a method thereof. The system comprises a current sensor, a determination circuit, and a current mirror circuit. The current sensor, coupled to the load, produces a current indication indicating the current. The determination circuit, coupled to the current sensor, generates a short-circuit signal when the current exceeds a predetermined threshold. The current mirror circuit, coupled to a voltage source, the current sensor and the determination circuit, comprises a current mirror and a bypass path, delivers a mirrored current from the current mirror to the load upon receiving the short-circuit signal, and passes the current from the voltage source through the bypass path to the load in the absence of the short-circuit signal.

摘要翻译： 能够限制通过负载的电流的系统及其方法。 该系统包括电流传感器，确定电路和电流镜电路。 耦合到负载的电流传感器产生指示电流的电流指示。 耦合到电流传感器的确定电路当电流超过预定阈值时产生短路信号。 耦合到电压源的电流镜电路，电流传感器和确定电路包括电流镜和旁路路径，在接收到短路信号时将来自电流镜的镜像电流传送到负载，并且通过 在不存在短路信号的情况下，电压从电源通过旁通路径到负载。

公开(公告)号：US20060145732A1

公开(公告)日：2006-07-06

申请号：US11027966

申请日：2005-01-03

申请人： Chi-Ming Hsiao ,  Chang-Fu Kuo

发明人： Chi-Ming Hsiao ,  Chang-Fu Kuo

IPC分类号： H03B21/00

CPC分类号： H03L7/10 ,  H03D13/004 ,  H03L7/081 ,  H03L7/18

摘要： A fast-locking apparatus and method for frequency synthesis. A transition detector receives a first pulse signal indicative that the phase of an input signal leads that of a reference signal, receives a second pulse signal indicative that the phase of the input signal lags that of the reference signal, and generates a state signal indicative of whether the first pulse signal is ahead of the second pulse signal. A pulse-width detector generates a first width signal indicative of into which range the width of the first pulse signal falls; another pulse-width detector generates a second width signal indicative of into which range the width of the second pulse signal falls. According to the state signal and the first and the second width signals, control logic generates a regulation signal for use in adjusting the frequency of the input signal.

公开(公告)号：US20090227222A1

公开(公告)日：2009-09-10

申请号：US12041664

申请日：2008-03-04

申请人： Chao-Hsin Lu ,  Chang-Fu Kuo

发明人： Chao-Hsin Lu ,  Chang-Fu Kuo

IPC分类号： H04B1/06

CPC分类号： G01S19/23 ,  H03G3/3052

摘要： A wireless receiver with automatic gain control and a method for automatic gain control of a receiving circuit utilized in a wireless receiver are provided. The receiving circuit includes a programmable gain amplifier and a low noise amplifier, and the method includes: comparing a gain code of the programmable gain amplifier with a predetermined code range, wherein the gain code is determined by a frequency signal received through the low noise amplifier; and adjusting a gain of the low noise amplifier when the gain code is out of the predetermined code range.

摘要翻译： 提供一种具有自动增益控制的无线接收机和用于无线接收机中的接收电路的自动增益控制方法。 接收电路包括可编程增益放大器和低噪声放大器，该方法包括：将可编程增益放大器的增益代码与预定代码范围进行比较，其中增益代码由通过低噪声放大器接收的频率信号确定 ; 以及当所述增益代码超出所述预定代码范围时调整所述低噪声放大器的增益。

公开(公告)号：US07363013B2

公开(公告)日：2008-04-22

申请号：US10693962

申请日：2003-10-28

申请人： Chang-Fu Kuo ,  Ling-Wei Ke ,  Jen-Chiou Bo ,  Shou-Tsung Wang ,  Kuang-Kai Teng

发明人： Chang-Fu Kuo ,  Ling-Wei Ke ,  Jen-Chiou Bo ,  Shou-Tsung Wang ,  Kuang-Kai Teng

IPC分类号： H04B1/04

CPC分类号： H03C3/0983 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0966

摘要： A phase lock loop receives a baseband signal which has an input frequency, and modulating the baseband signal to be a corresponding RF signal which has a predetermined transmission frequency for transmitting. The phase lock loop comprises a programmable divider, a modulator, a phase detector, a charging pump, a loop filter, a voltage-controlled oscillator and a frequency converter. The programmable divider divides the frequency of a local oscillating signal by a programmable divisor to generate a reference signal. The modulator receives the baseband signal, modulates the frequency of the reference signal according to the baseband signal, and generates a corresponding first comparison signal. The frequency converter receives the feedback RF signal and the local oscillating signal and outputs the second comparison signal according to the frequency difference. The divisor of the divider is programmable to avoid the spur frequency being generated because the local oscillating signal is interfered.

摘要翻译： 锁相环接收具有输入频率的基带信号，并且将基带信号调制为具有用于发送的预定发送频率的对应的RF信号。 锁相环包括可编程分频器，调制器，相位检测器，充电泵，环路滤波器，压控振荡器和变频器。 可编程分频器通过可编程除数器对本地振荡信号的频率进行分频，以产生参考信号。 调制器接收基带信号，根据基带信号调制参考信号的频率，并产生相应的第一比较信号。 变频器接收反馈RF信号和本地振荡信号，并根据频率差输出第二比较信号。 除法器的除数是可编程的，以避免由于本地振荡信号的干扰而产生的杂散频率。

公开(公告)号：US20060208804A1

公开(公告)日：2006-09-21

申请号：US11079220

申请日：2005-03-15

申请人： Chang-Fu Kuo ,  Po-Sen Tseng ,  Shou-Tsung Wang ,  Ling-Wei Ko

发明人： Chang-Fu Kuo ,  Po-Sen Tseng ,  Shou-Tsung Wang ,  Ling-Wei Ko

IPC分类号： H03L7/00

CPC分类号： H03L7/085 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/1072 ,  H03L7/18 ,  H03L7/185 ,  H03L2207/05

摘要： The invention provides a phase-locked loop (PLL). Since a loop bandwidth of the PLL is a function of a gain of a phase detector and a gain of a voltage controlled oscillator (VCO), by adjusting the gain of the phase detector, the variation of the gain of the VCO (i.e., the tuning sensitivity) is compensated, so that the loop bandwidth of the PLL becomes more stable.