Electronic circuit protector
    3.
    发明授权

    公开(公告)号:US11502510B2

    公开(公告)日:2022-11-15

    申请号:US17395741

    申请日:2021-08-06

    Applicant: Chao-Cheng Lu

    Inventor: Chao-Cheng Lu

    Abstract: The electronic circuit protector of the invention comprises a first semiconductor, a second semiconductor, a third semiconductor, a first diode, a second diode, a first resistor, a second resistor and a third resistor, constituting an application circuit with load overload or short circuit protection function, which avoids the damage caused by overload or short circuit at both terminals of the load.

    Method for Direct Manipulation and Visualization of the 3D Internal Structures of a Tubular Object as They are in Reality Without Any Noticeable Distortion

    公开(公告)号:US20220284685A1

    公开(公告)日:2022-09-08

    申请号:US17674004

    申请日:2022-02-17

    Abstract: In many applications, the assessment of the internal structures of tubular structures (such as in medical imaging, blood vessels, bronchi, and colon) has become a topic of high interest. Many 3D visualization techniques, such as “fly-through” and curved planar reformation (CPR), have been used for visualization of the lumens for medical applications. However, all the existing visualization techniques generate highly distorted images of real objects. This invention provides direct manipulation based on the centerline of the object and visualization of the 3D internal structures of a tubular object without any noticeable distortion. For the first time ever, the lumens of a human colon is visualized as it is in reality. In many medical applications, this can be used for diagnosis, planning of surgery or stent placements, etc. and consequently improves the quality of healthcare significantly. The same technique can be used in many other applications.

    METHOD FOR USING SEMICONDUCTOR INTELLIGENCE LINE

    公开(公告)号:US20220271525A1

    公开(公告)日:2022-08-25

    申请号:US17539621

    申请日:2021-12-01

    Applicant: CHAO-CHENG LU

    Inventor: CHAO-CHENG LU

    Abstract: The method for using semiconductor intelligence line of the invention, which is to set the semiconductor intelligence line on the drain source voltage axis of the first semiconductor output characteristic, has a gate voltage setting, which indicates the function of limiting the application limit of the drain source current on the output characteristic.

    Remote Automatic Control Power Supply System

    公开(公告)号:US20210157377A1

    公开(公告)日:2021-05-27

    申请号:US16697262

    申请日:2019-11-27

    Applicant: Chao-Cheng YU

    Inventor: Chao-Cheng YU

    Abstract: A remote automatic control power supply system is disclosed, comprising a power supply control device and an electronic device having a control circuit, in which the power supply control device is configured to control whether the power supply is to be outputted, and the control circuit can set the GPS coordinate and the starting distance value close to the power supply control device; afterwards, it is possible to operate the control circuit via the backend of the electronic device such that, when the distance between the real-time GPS coordinate of the electronic device and the GPS coordinate of the power supply control device is equivalent to the starting distance value, the control circuit can transmit a power control signal to the power supply control device thereby allowing the power supplying control device to output the electric power to the receiving end.

    PROTECTION LAYER AND METHOD FOR MAKING THE SAME

    公开(公告)号:US20210028331A1

    公开(公告)日:2021-01-28

    申请号:US16932829

    申请日:2020-07-20

    Abstract: A protection layer for use in fabrication of failure analysis (FA) sample is disclosed, which principally comprises a first thin film, a buffer thin film and a second thin film By forming the protection layer on a surface of a malfunction device die, a FA sample of the malfunction device die is obtained. As a result, in the case of treating the sample with a FIB thinning process, there are no cracks, distortion, and/or collapse resulted from inter-elemental isobaric interferences, stress effect or charge accumulation occurring on the surface layer of the malfunction device die because of the protection of the protection layer. On the other hand, this protection layer can also be applied to a microLED element or a VCSEL element, so as to make microLED element and the VCSEL element possess excellent stress withstanding capability.

    Composite dummy gate with conformal polysilicon layer for FinFET device
    8.
    发明授权
    Composite dummy gate with conformal polysilicon layer for FinFET device 有权
    用于FinFET器件的具有适形多晶硅层的复合伪栅极

    公开(公告)号:US09287179B2

    公开(公告)日:2016-03-15

    申请号:US13353975

    申请日:2012-01-19

    Abstract: The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.

    Abstract translation: 本公开涉及FinFET。 FinFET包括在衬底上形成的翅片结构。 栅介质层最少部分地缠绕在翅片结构的一段上。 栅介质层包含高k栅介质材料。 FinFET包括在栅介质层上共形形成的多晶硅层。 FinFET包括在多晶硅层上形成的金属栅极电极层。 本公开提供了制造FinFET的方法。 该方法包括提供包含半导体材料的翅片结构。 该方法包括在鳍结构上方形成栅极电介质层,栅介质层至少部分地围绕翅片结构缠绕。 该方法包括在栅介质层上形成多晶硅层,其中多晶硅层以保形方式形成。 该方法包括在多晶硅层上形成伪栅极层。

    Lamp
    9.
    外观设计
    Lamp 有权

    公开(公告)号:USD743604S1

    公开(公告)日:2015-11-17

    申请号:US29482247

    申请日:2014-02-17

    Applicant: Chao-Cheng Kuo

    Designer: Chao-Cheng Kuo

    Light emitting mirror structure
    10.
    发明授权
    Light emitting mirror structure 有权
    发光镜结构

    公开(公告)号:US09170353B2

    公开(公告)日:2015-10-27

    申请号:US13937829

    申请日:2013-07-09

    Inventor: Chao-Cheng Chang

    Abstract: A light emitting mirror structure includes a casing caved in to form an accommodating space having a light guiding area and a mirror area, and at least one surface of the casing as a sidewall communicating with the accommodating space. The mirror structure includes a light guiding device having a light guide plate, and a light emitting member disposed on a side of the light guide plate, and the light guiding device is placed at the light guiding area of the accommodating space of the casing. A mirror body having a substrate and a mirror surface located on the substrate is provided for the disclosed mirror structure also. The mirror body is integrated on the mirror area of the accommodating space, the light guiding plate causes a light to be emitted through the sidewall at a first side of the mirror body, and the mirror surface is uncovered by the sidewall.

    Abstract translation: 发光镜结构包括:壳体,其形成具有导光区域和反射镜区域的容纳空间,以及与容纳空间连通的壳体的至少一个表面。 反射镜结构包括具有导光板的导光装置和设置在导光板一侧的发光部件,导光装置设置在壳体的容纳空间的导光区域。 为所公开的反射镜结构也提供了具有衬底和位于衬底上的镜面的镜体。 镜体整合在容纳空间的镜面上,导光板在镜体的第一侧通过侧壁发射光,并且镜面未被侧壁覆盖。

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