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    Composite dummy gate with conformal polysilicon layer for FinFET device
    1.
    发明授权
    Composite dummy gate with conformal polysilicon layer for FinFET device 有权
    用于FinFET器件的具有适形多晶硅层的复合伪栅极

    公开(公告)号：US09287179B2

    公开(公告)日：2016-03-15

    申请号：US13353975

    申请日：2012-01-19

    Applicant: Yuan-Sheng Huang ,  Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chao-Cheng Chen ,  Chia-Jen Chen

    Inventor： Yuan-Sheng Huang ,  Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chao-Cheng Chen ,  Chia-Jen Chen

    IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

    CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

    Abstract: The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.

    Abstract translation: 本公开涉及FinFET。 FinFET包括在衬底上形成的翅片结构。 栅介质层最少部分地缠绕在翅片结构的一段上。 栅介质层包含高k栅介质材料。 FinFET包括在栅介质层上共形形成的多晶硅层。 FinFET包括在多晶硅层上形成的金属栅极电极层。 本公开提供了制造FinFET的方法。 该方法包括提供包含半导体材料的翅片结构。 该方法包括在鳍结构上方形成栅极电介质层，栅介质层至少部分地围绕翅片结构缠绕。 该方法包括在栅介质层上形成多晶硅层，其中多晶硅层以保形方式形成。 该方法包括在多晶硅层上形成伪栅极层。

    Mask and method for forming the same
    3.
    发明授权
    Mask and method for forming the same 有权
    面具及其形成方法

    公开(公告)号：US08974988B2

    公开(公告)日：2015-03-10

    申请号：US13451767

    申请日：2012-04-20

    Applicant: Yun-Yue Lin ,  Ta-Cheng Lien ,  Hsin-Chang Lee ,  Anthony Yen ,  Chia-Jen Chen

    Inventor： Yun-Yue Lin ,  Ta-Cheng Lien ,  Hsin-Chang Lee ,  Anthony Yen ,  Chia-Jen Chen

    IPC: G03F1/48

    CPC classification number: G03F1/48 ,  G03F1/22 ,  G03F1/26 ,  G03F1/30 ,  G03F1/32 ,  G03F1/50

    Abstract: A photomask includes a low thermal expansion material (LTEM) substrate, a patterned opaque layer over the LTEM substrate, and a patterned capping layer over the opaque layer. The patterned capping layer includes a transition metal material for suppressing haze growth, such as metal oxide, metal nitride, or metal oxynitride. The material in the capping layer reacts with a hydrogenic compound from a lithography environment to for an atomic level hydrogen passivation layer. The passivation layer has superior ability to suppress photo-induced haze defect growth on the photomask surface, to improve production cycle time and reduce the production cost.

    Abstract translation: 光掩模包括低热膨胀材料（LTEM）衬底，在LTEM衬底上的图案化不透明层，以及在不透明层上的图案化覆盖层。 图案化覆盖层包括用于抑制雾度生长的过渡金属材料，例如金属氧化物，金属氮化物或金属氮氧化物。 覆盖层中的材料与来自光刻环境的氢化合物与原子级氢钝化层反应。 钝化层在光掩模表面上具有优异的抑制光致霾缺陷生长的能力，提高生产周期时间，降低生产成本。

    Photomask and method for forming the same
    4.
    发明授权
    Photomask and method for forming the same 有权
    光掩模及其形成方法

    公开(公告)号：US08962222B2

    公开(公告)日：2015-02-24

    申请号：US13495291

    申请日：2012-06-13

    Applicant: Hsin-Chang Lee ,  Pei-Cheng Hsu ,  Chia-Jen Chen ,  Anthony Yen

    Inventor： Hsin-Chang Lee ,  Pei-Cheng Hsu ,  Chia-Jen Chen ,  Anthony Yen

    IPC: G03F1/00 ,  G03F1/44 ,  G03F1/24 ,  G03F1/68 ,  G03F1/76

    CPC classification number: G03F1/76 ,  G03F1/24 ,  G03F1/38 ,  G03F1/44 ,  G03F1/50 ,  G03F1/68 ,  G03F1/70 ,  G06F17/5068

    Abstract: A photomask having a machine-readable identifying mark and suitable for manufacturing integrated circuit devices and a method for forming the photomask and identifying mark are disclosed. An exemplary embodiment includes receiving a design layout corresponding to a pattern to be formed on a photomask blank. A specification of an identifying code is also received along with the photomask blank, which includes a substrate, a reflective layer, and an absorptive layer. A first patterning is performed using the design layout. A second patterning is performed using the specification of the identifying code.

    Abstract translation: 公开了一种具有机读识别标记并适于制造集成电路器件的光掩模和用于形成光掩模和识别标记的方法。 示例性实施例包括接收与在光掩模坯件上形成的图案相对应的设计布局。 识别码的规格也与包括基底，反射层和吸收层的光掩模坯料一起被接收。 使用设计布局进行第一图案化。 使用识别码的说明来执行第二图案化。

    Systems and methods for lithography masks
    7.
    发明授权
    Systems and methods for lithography masks 有权
    光刻掩模的系统和方法

    公开(公告)号：US08785083B2

    公开(公告)日：2014-07-22

    申请号：US13486015

    申请日：2012-06-01

    Applicant: Chih-Chiang Tu ,  Hsin-Chang Lee ,  Jong-Yuh Chang ,  Chia-Jen Chen ,  Chun-Lang Chen

    Inventor： Chih-Chiang Tu ,  Hsin-Chang Lee ,  Jong-Yuh Chang ,  Chia-Jen Chen ,  Chun-Lang Chen

    IPC: G03F1/00

    CPC classification number: G03F1/36 ,  G03F1/50 ,  G03F1/58 ,  G03F1/80

    Abstract: Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.

    Abstract translation: 公开了掩模毛坯和掩模的结构，以及制造掩模的方法。 当过程经过蚀刻步骤三次时，新的掩模坯料和掩模包括三层蚀刻停止层，以防止损坏石英基板。 三重蚀刻停止层可以包括含有氮（TaN）的钽的第一子层，含有氧（TaO）的钽的第二子层和TaN的第三子层。 或者，三重蚀刻停止层可以包括SiON材料的第一子层，TaO材料的第二子层和SiON材料的第三子层。 另一个替代方案可以是一层低蚀刻速率的MoxSiyONz材料，当该工艺经过蚀刻步骤三次时，其可以防止对石英衬底的损坏。 通过使用各种光学邻近校正规则在掩模空白上定义岛掩模。

    Semiconductor structure having a polysilicon structure and method of forming same
    8.
    发明授权
    Semiconductor structure having a polysilicon structure and method of forming same 有权
    具有多晶硅结构的半导体结构及其形成方法

    公开(公告)号：US08574989B2

    公开(公告)日：2013-11-05

    申请号：US13314462

    申请日：2011-12-08

    Applicant: Che-Cheng Chang ,  Po-Chi Wu ,  Buh-Kuan Fang ,  Jr-Jung Lin ,  Ryan Chia-Jen Chen

    Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Buh-Kuan Fang ,  Jr-Jung Lin ,  Ryan Chia-Jen Chen

    IPC: H01L21/336

    CPC classification number: H01L21/28114 ,  H01L21/02071 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/7843

    Abstract: The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure.

    Abstract translation: 本申请公开了一种形成半导体结构的方法。 在至少一个实施例中，该方法包括在衬底上形成多晶硅层。 在多晶硅层上形成掩模层。 图案化掩模层以形成图案化掩模层。 通过使用图案化掩模层作为掩模蚀刻多晶硅层来形成多晶硅结构。 多晶硅结构具有上表面和下表面，并且多晶硅层的蚀刻被布置成使得多晶硅结构的上表面的宽度大于多晶硅结构的下表面的宽度。

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