公开(公告)号：US06725358B1

公开(公告)日：2004-04-20

申请号：US09598435

申请日：2000-06-22

申请人： Charles Robert Moore

发明人： Charles Robert Moore

IPC分类号： G06F9312

CPC分类号： G06F9/383 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3824

摘要： A processor includes a register set, at least one execution unit that executes load instructions to transfer data into the register set, a load queue and associated queue management logic. The load queue contains a plurality of entries that each include a reservation valid field, and each of the plurality of entries is associated with a respective one of a corresponding plurality of load instructions that includes at least one load-reserve instruction. In response to execution of the load-reserve instruction, the queue management logic detects whether a data hazard exists by reference to the load queue, and if so, initiates correction of the data hazard. In addition, the queue management logic records a reservation for the load-reserve instruction by setting the reservation valid field of an entry in the load queue associated with the load-reserve instruction. Thus, the load queue, which is utilized to detect and correct data hazards resulting from out-of-order execution of load instructions, is also advantageously utilized to manage reservations.

摘要翻译： 处理器包括一个寄存器组，至少一个执行单元，其执行将数据传送到寄存器集合中的加载指令，负载队列和相关联的队列管理逻辑。 加载队列包含多个条目，每个条目包括预留有效字段，并且多个条目中的每一个条目与包括至少一个加载保留指令的对应多个加载指令中的相应一个相关联。 响应于负载保留指令的执行，队列管理逻辑通过参考负载队列来检测是否存在数据危害，如果是，则发起对数据危害的更正。 此外，队列管理逻辑通过设置与加载备用指令相关联的加载队列中的条目的预留有效字段来记录加载保留指令的预留。 因此，用于检测和纠正由于加载指令的无序执行而导致的数据危害的负载队列也有利地用于管理预留。

公开(公告)号：US06871273B1

公开(公告)日：2005-03-22

申请号：US09598436

申请日：2000-06-22

申请人： Charles Robert Moore

发明人： Charles Robert Moore

IPC分类号： G06F9/00 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/3017 ,  G06F9/3824

摘要： A processor implementing an improved method for executing load instructions includes execution circuitry, a plurality of registers, and instruction processing circuitry. The instruction processing circuitry fetches a load instruction and a preceding instruction that precedes the load instruction in program order, and in response to detecting the load instruction, translates the load instruction into separately executable prefetch and register operations. The execution circuitry performs at least the prefetch operation out-of-order with respect to the preceding instruction to prefetch data into the processor and subsequently separately executes the register operation to place the data into a register specified by the load instruction. In an embodiment in which the processor is an in-order machine, the register operation is performed in-order with respect to the preceding instruction.

摘要翻译： 实施用于执行加载指令的改进方法的处理器包括执行电路，多个寄存器和指令处理电路。 指令处理电路以程序顺序读取加载指令和先前的指令，并且响应于检测到加载指令，将加载指令转换成单独的可执行预取和寄存器操作。 执行电路至少执行关于先前指令的预取操作，以将数据预取到处理器中，并且随后分别执行寄存器操作以将数据放入由加载指令指定的寄存器中。 在处理器是按顺序的机器的实施例中，相对于前一个指令按顺序执行寄存器操作。

公开(公告)号：US06715062B1

公开(公告)日：2004-03-30

申请号：US09626248

申请日：2000-07-26

申请人： Charles Robert Moore

发明人： Charles Robert Moore

IPC分类号： G06F944

CPC分类号： G06F9/3017 ,  G06F9/30003 ,  G06F9/30076 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3861 ,  G06F11/2236

摘要： A processor includes instruction sequencing logic, execution circuitry, data storage coupled to the execution circuitry, and test circuitry. The test circuitry detects for a hardware error in one of the instruction sequencing logic, execution circuitry, and data storage during functional operation of the processor in response to an instruction within an instruction stream provided by the instruction sequencing logic. In one embodiment, a hardware error can be detected by comparing values output in response to a test instruction by redundant circuitry that performs the same function. Alternatively or in addition, a hardware error can be detected by performing an arithmetic or logical operation having a known result (e.g., multiplication by 1, addition of 0, etc.) in response to the test instruction.

摘要翻译： 处理器包括指令排序逻辑，执行电路，耦合到执行电路的数据存储器和测试电路。 响应于由指令排序逻辑提供的指令流中的指令，测试电路在处理器的功能操作期间检测指令排序逻辑，执行电路和数据存储之一中的硬件错误。 在一个实施例中，可以通过执行相同功能的冗余电路比较响应于测试指令的输出值来检测硬件错误。 或者或另外，可以通过响应于测试指令执行具有已知结果（例如，乘以1，相加0等）的算术或逻辑运算来检测硬件错误。

公开(公告)号：US06704860B1

公开(公告)日：2004-03-09

申请号：US09626249

申请日：2000-07-26

申请人： Charles Robert Moore

发明人： Charles Robert Moore

IPC分类号： G06F944

CPC分类号： G06F9/3802 ,  G06F9/3824 ,  G06F9/3836

摘要： A data processing system and method of fetching instructions in a data processing system are described. The data processing system includes at least one execution unit that executes fetched instructions and instruction sequencing logic that fetches instructions from memory. In response to detection of a particular instruction trigger within an instruction stream, the instruction sequencing logic fetches one or more non-sequential blocks of instructions from memory, where each of the non-sequential blocks includes a plurality of instructions.

摘要翻译： 描述了在数据处理系统中取指令的数据处理系统和方法。 数据处理系统包括至少一个执行单元，执行取出的指令和从存储器取出指令的指令排序逻辑。 响应于检测到指令流内的特定指令触发，指令排序逻辑从存储器中取出一个或多个非顺序指令块，其中每个非顺序块包括多个指令。

公开(公告)号：US06868491B1

公开(公告)日：2005-03-15

申请号：US09598434

申请日：2000-06-22

申请人： Charles Robert Moore

发明人： Charles Robert Moore

IPC分类号： G06F9/312 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3889

摘要： A processor having a reduced data hazard penalty includes a register set, at least one execution unit that executes load instructions to transfer data into the register set, and a load queue. The load queue contains at least one entry, and each occupied entry in the load queue stores load data retrieved by an executed load instruction in association with a target address of the executed load instruction. The load queue has associated queue management logic that, in response to execution by the execution unit of a load instruction, determines by reference to the load queue whether a data hazard exists for the load instruction. If so, the queue management logic outputs load data from the load queue to the register set in accordance with the load instruction, thus eliminating the need to flush and re-execute the load instruction.

摘要翻译： 具有减少的数据危险损失的处理器包括寄存器组，至少一个执行单元，其执行将数据传送到寄存器组的加载指令和负载队列。 加载队列包含至少一个条目，并且加载队列中的每个占用条目将由执行的加载指令检索的加载数据与执行的加载指令的目标地址相关联。 负载队列具有相关联的队列管理逻辑，其响应于执行单元执行加载指令，通过参考加载队列来确定是否存在用于加载指令的数据危险。 如果是这样，则队列管理逻辑根据加载指令将负载数据从负载队列输出到寄存器组，因此不需要刷新并重新执行加载指令。

公开(公告)号：US06829702B1

公开(公告)日：2004-12-07

申请号：US09626247

申请日：2000-07-26

申请人： Thomas Leo Jeremiah ,  Charles Robert Moore

发明人： Thomas Leo Jeremiah ,  Charles Robert Moore

IPC分类号： G06F932

CPC分类号： G06F9/381 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3885

摘要： A processor that efficiently obtains target path instructions in the presence of tight program loops includes at least one execution unit for executing instructions and instruction sequencing logic that supplies instructions to the at least one execution unit for execution. The instruction sequencing logic includes an instruction fetch buffer and a branch prediction unit including a branch target cache. In response to prediction of a branch instruction as taken, the branch target cache causes multiple copies of a target instruction group to be loaded into the instruction fetch buffer under the assumption that the branch instruction is a member of the target instruction group. Thereafter, the branch target cache causes all but one of the multiple copies to be canceled from the instruction fetch buffer prior to dispatch if the branch instruction does not belong to the target instruction group. Thus, the branch target cache can meet the instruction fetch cycle time of the processor even for the worst case condition in which the branch instruction is within the target instruction group.

摘要翻译： 在存在紧密程序循环的情况下有效地获得目标路径指令的处理器包括至少一个执行单元，用于执行向至少一个执行单元提供指令以执行的指令和指令排序逻辑。 指令排序逻辑包括指令获取缓冲器和包括分支目标高速缓存的分支预测单元。 响应于如所采用的分支指令的预测，在假设分支指令是目标指令组的成员的假设下，分支目标高速缓存使目标指令组的多个副本被加载到指令获取缓冲器中。 此后，如果分支指令不属于目标指令组，则分支目标高速缓存使得在分派之前从指令获取缓冲器中取消多个副本中的一个副本。 因此，即使在分支指令在目标指令组内的最坏情况条件下，分支目标高速缓存也可以满足处理器的指令获取周期时间。