公开(公告)号：US20180193761A1

公开(公告)日：2018-07-12

申请号：US15432948

申请日：2017-02-15

申请人： CHENG-HUA HAN

发明人： CHENG-HUA HAN

IPC分类号： A63H33/04 ,  A63H33/10

CPC分类号： A63H33/044 ,  A63H33/10 ,  A63H33/107 ,  A63H33/108

摘要： A set of castle building blocks comprising a plurality of brick units, city wall units, cylinder units, tower units, and connection units. All of the units excluded the connection units have at least two blind holes. Each connection unit includes a rod section and a head section connected with each other. The rod section inserts into the corresponding blind hole. The head section detachably inserts into the blind hole of one of the units excluded the connection units. A plurality of convex arc portions is inclined and extended upwardly and outwardly from the rod section axially. The head section includes a main body, a hollow portion, and a concave groove. The concave groove of the connection unit is arranged so that the main body of the head section has a space to elastically insert into the blind hole of other unit excluded the connection units.

公开(公告)号：US09105493B2

公开(公告)日：2015-08-11

申请号：US13476019

申请日：2012-05-21

申请人： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Te-Yuan Wu

发明人： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

CPC分类号： H01L29/0878 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7816

摘要： A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region further includes a plurality of third doped regions, a plurality of gaps, and a plurality of fourth doped regions. The gaps and the third doped regions s are alternately arranged, and the fourth doped regions are formed in the gaps. The third doped regions include a second conductivity type complementary to the first conductivity type, and the fourth doped regions include the first conductivity type.

摘要翻译： 高电压金属氧化物半导体晶体管器件的布局图案包括具有第一导电类型的第一掺杂区域，具有第一导电类型的第二掺杂区域和形成在第一掺杂区域和第二掺杂区域之间的非连续掺杂区域 第二掺杂区域。 非连续掺杂区还包括多个第三掺杂区，多个间隙和多个第四掺杂区。 间隙和第三掺杂区域交替排列，并且第四掺杂区域形成在间隙中。 第三掺杂区域包括与第一导电类型互补的第二导电类型，并且第四掺杂区域包括第一导电类型。

公开(公告)号：US08686821B2

公开(公告)日：2014-04-01

申请号：US13526534

申请日：2012-06-19

申请人： Yung-Chung Chang ,  Meng-Sheng Chen ,  Chang-Chih Liu ,  Li-Chi Chang ,  Cheng-Hua Tsai

发明人： Yung-Chung Chang ,  Meng-Sheng Chen ,  Chang-Chih Liu ,  Li-Chi Chang ,  Cheng-Hua Tsai

IPC分类号： H01F21/02 ,  H01F27/28

CPC分类号： H01F17/0013 ,  H01F2017/004

摘要： An inductor structure including a plurality of solenoids and at least one connecting line is provided. One of the solenoids serves as a core, and the remaining solenoids are sequentially wound around the core solenoid. Axes of the solenoids are substantially directed to the same direction. Each connecting line is correspondingly connected between ends of two adjacent solenoids to serially connect the solenoids.

摘要翻译： 提供包括多个螺线管和至少一个连接线的电感器结构。 螺线管中的一个用作芯，并且剩余的螺线管顺序缠绕在磁芯螺线管周围。 螺线管的轴基本上指向相同的方向。 每个连接线相应地连接在两个相邻螺线管的端部之间，以串联连接螺线管。

公开(公告)号：US20130307071A1

公开(公告)日：2013-11-21

申请号：US13476019

申请日：2012-05-21

申请人： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Te-Yuan Wu

发明人： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7816

摘要： A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region further includes a plurality of third doped regions, a plurality of gaps, and a plurality of fourth doped regions. The gaps and the third doped regions s are alternately arranged, and the fourth doped regions are formed in the gaps. The third doped regions include a second conductivity type complementary to the first conductivity type, and the fourth doped regions include the first conductivity type.

摘要翻译： 高电压金属氧化物半导体晶体管器件的布局图案包括具有第一导电类型的第一掺杂区域，具有第一导电类型的第二掺杂区域和形成在第一掺杂区域和第二掺杂区域之间的非连续掺杂区域 第二掺杂区域。 非连续掺杂区还包括多个第三掺杂区，多个间隙和多个第四掺杂区。 间隙和第三掺杂区域交替排列，并且第四掺杂区域形成在间隙中。 第三掺杂区域包括与第一导电类型互补的第二导电类型，并且第四掺杂区域包括第一导电类型。

公开(公告)号：US08432359B2

公开(公告)日：2013-04-30

申请号：US11970409

申请日：2008-01-07

申请人： Chuan-Kung Hou ,  Cheng-Hua Hsu

发明人： Chuan-Kung Hou ,  Cheng-Hua Hsu

IPC分类号： G06F3/033 ,  G09G5/08

CPC分类号： G06F3/03543 ,  G06F2203/0332 ,  G06F2203/0333

摘要： An ergonomic mouse has a sliding cap matching the curvature of a normal human palm. The sliding cap may be slid on the top of a hollow body to reach a desired operation position, then fine-tuned and anchored. Thus when the mouse is moved during operation, it can absorb reaction forces to avoid hurting the user's wrist and better meet ergonomic requirements.

摘要翻译： 符合人体工程学的鼠标具有与正常人类手掌的曲率相匹配的滑盖。 滑动盖可以在中空体的顶部上滑动以达到期望的操作位置，然后进行微调和锚定。 因此，当鼠标在操作过程中移动时，它可以吸收反作用力，以避免伤害使用者的手腕，更好地符合人体工程学的要求。

公开(公告)号：US20110170428A1

公开(公告)日：2011-07-14

申请号：US12687188

申请日：2010-01-14

申请人： Cheng-Hua Wang ,  Huiling Gong

发明人： Cheng-Hua Wang ,  Huiling Gong

IPC分类号： H04L12/26

CPC分类号： H04L45/46 ,  H04L45/12

摘要： Systems, methods, and other embodiments associated with generating a network buffer are provided. A network data model is input that includes a set of network elements, such as nodes and links, and respective costs associated with respective network elements. A center network element around which to generate the network buffer and an offset cost to define a boundary of the network buffer are also input. A network buffer is generated by determining a buffer coverage and cost. The network buffer is made up of a set of buffer network elements located within the offset cost with respect to the center network element. The cost for each buffer network element is determined as the cost associated with travelling a path with minimum cost from the center network element to the corresponding buffer network element. The buffer coverage and costs are output for subsequent analysis.

摘要翻译： 提供了与生成网络缓冲器相关联的系统，方法和其他实施例。 输入网络数据模型，其包括诸如节点和链路的一组网络元件以及与各个网络元件相关联的相应成本。 还输入了用于生成网络缓冲器的中心网络元件和用于定义网络缓冲器的边界的偏移成本。 通过确定缓冲区覆盖和成本来生成网络缓冲区。 网络缓冲器由位于相对于中心网络元件的偏移成本内的一组缓冲器网络元件组成。 将每个缓冲器网络元件的成本确定为与从中心网络元件到相应的缓冲器网络元件以最小成本行进路径相关联的成本。 输出缓冲区覆盖和成本用于后续分析。

公开(公告)号：US20110169597A1

公开(公告)日：2011-07-14

申请号：US13009432

申请日：2011-01-19

申请人： Chang-Lin Wei ,  Kuo-Chiang Chin ,  Cheng-Hua Tsai ,  Chin-Sun Shyu ,  Chang-Sheng Chen

发明人： Chang-Lin Wei ,  Kuo-Chiang Chin ,  Cheng-Hua Tsai ,  Chin-Sun Shyu ,  Chang-Sheng Chen

IPC分类号： H01F5/00

CPC分类号： H01F17/0013 ,  H01F17/02 ,  H01F30/08 ,  H01F2017/002 ,  H01F2017/0046

摘要： An inductor device comprising a first conductive pattern on a first layer of a substrate, a second conductive pattern on a second layer of the substrate, and a first region between the first layer and the second layer through which at least one hole is coupled between the first dielectric layer and the second dielectric layer, wherein a magnetic field induced by at least one of the first conductive pattern or the second conductive pattern at the first region is more intensive than that induced by at least one of the first conductive pattern or the second conductive pattern at a second region between the first conductive layer and the second conductive layer.

摘要翻译： 一种电感器装置，包括在衬底的第一层上的第一导电图案，在衬底的第二层上的第二导电图案，以及在第一层和第二层之间的第一区域，至少一个孔通过该第一区耦合在 第一电介质层和第二介电层，其中由第一区域中的第一导电图案或第二导电图案中的至少一个感应的磁场比由第一导电图案或第二介电层中的至少一个所诱发的磁场更加密集 导电图案在第一导电层和第二导电层之间的第二区域。

公开(公告)号：US20110139076A1

公开(公告)日：2011-06-16

申请号：US12821835

申请日：2010-06-23

申请人： YUEH-JU PU ,  Ming-Chang Teng ,  Ching-Yi Kuo ,  Cheng-Hua Wu

发明人： YUEH-JU PU ,  Ming-Chang Teng ,  Ching-Yi Kuo ,  Cheng-Hua Wu

IPC分类号： A01K29/00

CPC分类号： A01K5/0114 ,  A01K5/02 ,  A01K5/0291

摘要： An intelligent pet-feeding device is disclosed, which comprises: a frame, configured with at least one opening; a storage tank, for storing at least one kind of food while enabling each kind of food to be transported out of the frame from it corresponding opening; a communication module, capable of performing a wireless communication with an operator at a remote end; an imaging module, for capturing images and thus generating image signals accordingly; an audio transceiver module, for receiving and transmitting audio signals; and a central processing unit, electrically connected to the communication module, the imaging module and the audio transceiver module for processing signals received thereby and generated therefrom.

摘要翻译： 公开了一种智能宠物喂养装置，其包括：框架，其配置有至少一个开口; 存储罐，用于储存至少一种食物，同时使每种食物能够从相应的开口运出框架; 通信模块，能够与远端的操作者进行无线通信; 成像模块，用于捕获图像，从而相应地产生图像信号; 用于接收和发送音频信号的音频收发器模块; 以及电连接到通信模块，成像模块和音频收发器模块的中央处理单元，用于处理由此产生的信号并由其产生。

公开(公告)号：US07948355B2

公开(公告)日：2011-05-24

申请号：US11852244

申请日：2007-09-07

申请人： Chang-Lin Wei ,  Chang-Sheng Chen ,  Cheng-Hua Tsai ,  Syun Yu ,  Chin-Sun Shyu

发明人： Chang-Lin Wei ,  Chang-Sheng Chen ,  Cheng-Hua Tsai ,  Syun Yu ,  Chin-Sun Shyu

IPC分类号： H01C1/012

CPC分类号： H05K1/167 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/09781

摘要： An embedded resistor device includes a resistor, a ground plane located near a first side of the resistor and electrically coupled to a first end of the resistor, at the ground plane a hole is provided, a first dielectric layer exists between the resistor and the ground plane, a conductive wire, which is electrically coupled to a second end of the resistor different from the first end of the resistor and partially surrounds the resistor, is used as an auxiliary for supporting a resistor-coating process of the resistor and to provide a terminal of the embedded resistor device at the conductive wire, a conductive region located near a second side of the ground plane different from the first side of the resistor, a second dielectric layer exists between the ground plane and the conductive region, and a conductive path to electrically couple the conductive wire to the conductive region through the hole.

摘要翻译： 嵌入式电阻器件包括电阻器，接地平面位于电阻器的第一侧附近并电耦合到电阻器的第一端，在接地平面处设有一个孔，第一电介质层位于电阻器和地之间 平面，电耦合到电阻器的不同于电阻器的第一端并部分地围绕电阻器的第二端的导线被用作支持电阻器的电阻器涂覆工艺的辅助件，并且提供 在导电线处的嵌入式电阻器件的端子，位于接地平面的与电阻器的第一侧不同的第二侧附近的导电区域，在接地平面和导电区域之间存在第二介电层，并且导电路径 以通过该孔将导线电连接到导电区域。

公开(公告)号：USD635290S1

公开(公告)日：2011-03-29

申请号：US29345848

申请日：2009-10-22

申请人： Feng-Ting Hsu ,  Ming-Cheng Hua

设计人： Feng-Ting Hsu ,  Ming-Cheng Hua