公开(公告)号：US20140001607A1

公开(公告)日：2014-01-02

申请号：US13539160

申请日：2012-06-29

Applicant: Cheng-Chi CHUANG ,  Kun-Ming HUANG ,  Hsuan-Hui HUNG ,  Ming-Yi LIN

Inventor： Cheng-Chi CHUANG ,  Kun-Ming HUANG ,  Hsuan-Hui HUNG ,  Ming-Yi LIN

IPC: H01L29/02 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L21/02271 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer formed over the bottom dielectric layer for passivation, and a top dielectric layer formed over the doped dielectric layer for passivation.

Abstract translation: 集成电路包括衬底和钝化层。 钝化层包括在用于钝化的衬底上形成的底部电介质层，在用于钝化的底部电介质层上形成的掺杂电介质层，以及形成在掺杂介质层上用于钝化的顶部电介质层。

公开(公告)号：US08884405B2

公开(公告)日：2014-11-11

申请号：US13539160

申请日：2012-06-29

Applicant: Cheng-Chi Chuang ,  Kun-Ming Huang ,  Hsuan-Hui Hung ,  Ming-Yi Lin

Inventor： Cheng-Chi Chuang ,  Kun-Ming Huang ,  Hsuan-Hui Hung ,  Ming-Yi Lin

IPC: H01L23/58

CPC classification number: H01L21/02271 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer formed over the bottom dielectric layer for passivation, and a top dielectric layer formed over the doped dielectric layer for passivation.

Abstract translation: 集成电路包括衬底和钝化层。 钝化层包括在用于钝化的衬底上形成的底部电介质层，在用于钝化的底部电介质层上形成的掺杂电介质层，以及形成在掺杂介质层上用于钝化的顶部电介质层。

公开(公告)号：US20220285494A1

公开(公告)日：2022-09-08

申请号：US17750600

申请日：2022-05-23

Applicant: Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.

公开(公告)号：US08766357B2

公开(公告)日：2014-07-01

申请号：US13410135

申请日：2012-03-01

Applicant: Chao-Wei Tseng ,  Kun-Ming Huang ,  Cheng-Chi Chuang ,  Fu-Hsiung Yang

Inventor： Chao-Wei Tseng ,  Kun-Ming Huang ,  Cheng-Chi Chuang ,  Fu-Hsiung Yang

IPC: H01L29/66

CPC classification number: H01L29/7835 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.

Abstract translation: 高压MOS晶体管包括在衬底上形成的第一漏极/源极区域，形成在衬底上的第二漏极/源极区域和形成在衬底上的第一金属层。 第一金属层包括通过第一金属插塞耦合到第一漏极/源极区域的第一导体，通过第二金属插塞耦合到第二漏极/源极区域的第二导体和形成在第一导体之间的多个浮动金属环 和第二导体。 浮动金属环有助于提高高压MOS晶体管的击穿电压。

公开(公告)号：US20130228873A1

公开(公告)日：2013-09-05

申请号：US13410135

申请日：2012-03-01

Applicant: Chao-Wei Tseng ,  Kun-Ming Huang ,  Cheng-Chi Chuang ,  Fu-Hsiung Yang

Inventor： Chao-Wei Tseng ,  Kun-Ming Huang ,  Cheng-Chi Chuang ,  Fu-Hsiung Yang

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7835 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.

Abstract translation: 高压MOS晶体管包括在衬底上形成的第一漏极/源极区域，形成在衬底上的第二漏极/源极区域和形成在衬底上的第一金属层。 第一金属层包括通过第一金属插塞耦合到第一漏极/源极区域的第一导体，通过第二金属插塞耦合到第二漏极/源极区域的第二导体和形成在第一导体之间的多个浮动金属环 和第二导体。 浮动金属环有助于提高高压MOS晶体管的击穿电压。