Mute circuits
    1.
    发明授权
    Mute circuits 有权
    静音电路

    公开(公告)号:US08340320B2

    公开(公告)日:2012-12-25

    申请号:US12277438

    申请日:2008-11-25

    申请人: Chao-Wei Tseng

    发明人: Chao-Wei Tseng

    IPC分类号: H04R3/02

    CPC分类号: H03G3/348 H04R3/007 H04R3/04

    摘要: Mute circuits capable of eliminating audible noise when the audio system is powered up and powered down are disclosed. A discharge element is coupled between an audio processing unit and an audio output unit in an audio system and a mute control unit is coupled to the discharge element. The mute circuit comprises an active element comprising a control terminal coupled to at least one power voltage at a power terminal of a functional element in the audio processing unit through a capacitor and turning on, by AC capacitor coupling, to drive the discharge element when the audio system is powered up, such that the discharge element is turned on to discharge an output current of the audio processing unit to a ground terminal, thereby muting the audio output unit to eliminate audible noise.

    摘要翻译: 公开了当音频系统通电和掉电时能够消除可听见噪声的静音电路。 放电元件耦合在音频系统中的音频处理单元和音频输出单元之间,并且静音控制单元耦合到放电元件。 静音电路包括有源元件,其包括控制端子,该控制端子通过电容器耦合到音频处理单元中的功能元件的功率端子处的至少一个电源电压,并通过AC电容器耦合导通,以驱动放电元件 音频系统通电,使得放电元件接通以将音频处理单元的输出电流放电到接地端子,从而使音频输出单元静音以消除可听见的噪声。

    High voltage LDMOS transistor
    2.
    发明授权
    High voltage LDMOS transistor 有权
    高压LDMOS晶体管

    公开(公告)号:US08174071B2

    公开(公告)日:2012-05-08

    申请号:US12114439

    申请日:2008-05-02

    IPC分类号: H01L29/66

    摘要: An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of the extended gate electrode portion, the gate electrode further projects downwards into a convex-shaped recess or groove in the upper boundary of the extension dielectric region, forming a tongue. LDMOS transistors with this structure may provide improved suppression of hot carrier effects.

    摘要翻译: 提供LDMOS晶体管结构及其制造方法。 该结构包括在从LDMOS晶体管的漏极区域分离栅电极的延伸电介质区域的上边界上延伸的栅电极。 此外,在靠近延伸的栅极电极部分的边缘的区域,栅极电极还向下突出到延伸电介质区域的上边界中的凸形凹部或凹槽中,形成舌头。 具有这种结构的LDMOS晶体管可以提供对热载流子效应的改进的抑制。

    ELECTRONIC DEVICES WITH ENHANCED HEAT SPREADING
    3.
    发明申请
    ELECTRONIC DEVICES WITH ENHANCED HEAT SPREADING 审中-公开
    具有增强热传播的电子设备

    公开(公告)号:US20080080142A1

    公开(公告)日:2008-04-03

    申请号:US11763630

    申请日:2007-06-15

    IPC分类号: H05K7/20

    摘要: An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer.

    摘要翻译: 具有增强散热性的电子设备。 印刷电路板设置在壳体中,并且包括第一金属接地层,第二金属接地层和金属连接部分。 第一金属接地层与第二金属接地层相对。 金属连接部分连接在第一和第二金属接地层之间。 第二金属接地层连接到外壳。 芯片电连接到印刷电路板,并且包括模具和连接到模具并与第一金属接地层焊接的导热部分。 由芯片产生的热量通过导热部分,第一金属接地层,金属连接部分和第二金属接地层传导到壳体。

    ELECTRONIC DEVICES WITH ENHANCED HEAT SPREADING
    4.
    发明申请
    ELECTRONIC DEVICES WITH ENHANCED HEAT SPREADING 审中-公开
    具有增强热传播的电子设备

    公开(公告)号:US20090236707A1

    公开(公告)日:2009-09-24

    申请号:US12473477

    申请日:2009-05-28

    摘要: An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer.

    摘要翻译: 具有增强散热性的电子设备。 印刷电路板设置在壳体中,并且包括第一金属接地层,第二金属接地层和金属连接部分。 第一金属接地层与第二金属接地层相对。 金属连接部分连接在第一和第二金属接地层之间。 第二金属接地层连接到外壳。 芯片电连接到印刷电路板,并且包括模具和连接到模具并与第一金属接地层焊接的导热部分。 由芯片产生的热量通过导热部分,第一金属接地层,金属连接部分和第二金属接地层传导到壳体。

    Apparatus and method for high voltage MOS transistor
    5.
    发明授权
    Apparatus and method for high voltage MOS transistor 有权
    高压MOS晶体管的装置和方法

    公开(公告)号:US08766357B2

    公开(公告)日:2014-07-01

    申请号:US13410135

    申请日:2012-03-01

    IPC分类号: H01L29/66

    摘要: A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.

    摘要翻译: 高压MOS晶体管包括在衬底上形成的第一漏极/源极区域,形成在衬底上的第二漏极/源极区域和形成在衬底上的第一金属层。 第一金属层包括通过第一金属插塞耦合到第一漏极/源极区域的第一导体,通过第二金属插塞耦合到第二漏极/源极区域的第二导体和形成在第一导体之间的多个浮动金属环 和第二导体。 浮动金属环有助于提高高压MOS晶体管的击穿电压。

    Apparatus and Method for High Voltage MOS Transistor
    6.
    发明申请
    Apparatus and Method for High Voltage MOS Transistor 有权
    高压MOS晶体管的装置和方法

    公开(公告)号:US20130228873A1

    公开(公告)日:2013-09-05

    申请号:US13410135

    申请日:2012-03-01

    IPC分类号: H01L27/092 H01L21/8238

    摘要: A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.

    摘要翻译: 高压MOS晶体管包括在衬底上形成的第一漏极/源极区域,形成在衬底上的第二漏极/源极区域和形成在衬底上的第一金属层。 第一金属层包括通过第一金属插塞耦合到第一漏极/源极区域的第一导体,通过第二金属插塞耦合到第二漏极/源极区域的第二导体和形成在第一导体之间的多个浮动金属环 和第二导体。 浮动金属环有助于提高高压MOS晶体管的击穿电压。

    MUTE CIRCUITS
    7.
    发明申请
    MUTE CIRCUITS 有权
    静音电路

    公开(公告)号:US20100128886A1

    公开(公告)日:2010-05-27

    申请号:US12277438

    申请日:2008-11-25

    申请人: Chao-Wei TSENG

    发明人: Chao-Wei TSENG

    IPC分类号: H04R3/02

    CPC分类号: H03G3/348 H04R3/007 H04R3/04

    摘要: Mute circuits capable of eliminating audible noise when the audio system is powered up and powered down are disclosed. A discharge element is coupled between an audio processing unit and an audio output unit in an audio system and a mute control unit is coupled to the discharge element. The mute circuit comprises an active element comprising a control terminal coupled to at least one power voltage at a power terminal of a functional element in the audio processing unit through a capacitor and turning on, by AC capacitor coupling, to drive the discharge element when the audio system is powered up, such that the discharge element is turned on to discharge an output current of the audio processing unit to a ground terminal, thereby muting the audio output unit to eliminate audible noise.

    摘要翻译: 公开了当音频系统通电和掉电时能够消除可听见噪声的静音电路。 放电元件耦合在音频系统中的音频处理单元和音频输出单元之间,并且静音控制单元耦合到放电元件。 静音电路包括有源元件,其包括控制端子,该控制端子通过电容器耦合到音频处理单元中的功能元件的功率端子处的至少一个电源电压,并通过AC电容器耦合导通,以驱动放电元件 音频系统通电,使得放电元件接通以将音频处理单元的输出电流放电到接地端子,从而使音频输出单元静音以消除可听见的噪声。

    High Voltage LDMOS Transistor and Method
    8.
    发明申请
    High Voltage LDMOS Transistor and Method 有权
    高压LDMOS晶体管和方法

    公开(公告)号:US20090273029A1

    公开(公告)日:2009-11-05

    申请号:US12114439

    申请日:2008-05-02

    IPC分类号: H01L29/78

    摘要: An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of the extended gate electrode portion, the gate electrode further projects downwards into a convex-shaped recess or groove in the upper boundary of the extension dielectric region, forming a tongue. LDMOS transistors with this structure may provide improved suppression of hot carrier effects.

    摘要翻译: 提供LDMOS晶体管结构及其制造方法。 该结构包括在从LDMOS晶体管的漏极区域分离栅电极的延伸电介质区域的上边界上延伸的栅电极。 此外,在靠近延伸的栅极电极部分的边缘的区域,栅极电极还向下突出到延伸电介质区域的上边界中的凸形凹部或凹槽中,形成舌头。 具有这种结构的LDMOS晶体管可以提供对热载流子效应的改进的抑制。