公开(公告)号：US5651713A

公开(公告)日：1997-07-29

申请号：US538986

申请日：1995-10-05

Applicant: Jong Duk Lee ,  Cheon Kyu Lee ,  Ho Young An

Inventor： Jong Duk Lee ,  Cheon Kyu Lee ,  Ho Young An

IPC: H01L21/316 ,  G09F9/313 ,  H01J9/02 ,  H01J1/30

CPC classification number: H01J9/025

Abstract: The present invention provides a method for manufacturing a low voltage driven field emitter array, comprising steps of forming a thin buffer layer on a silicon substrate, making a pattern with lots of silicon nitride masks on the layer, oxidizing the upper part of the substrate and forming a relatively thick oxide layer onto the substrate except the part under the nitride masks, during which the thick oxide layer upheaves the edges of the nitride masks and extends inwardly under the nitride masks so that the edges of the thick oxide layer under the nitride masks may have a kind of bird's beak shape in cross section, etching away the nitride mask pattern, exposing the silicon substrate for the circular parts surrounded by the bird's beak shape edges by etching away the thin buffer layer, etching away the exposed substrate for making gate holes of undercut shape, and forming metal layers on the substrate and the bottom of the gate holes by evaporating a matalic evaporant downwardly and vertically against the surface of the substrate. The diameter of the gate hole is reduced in comparison to that defined by the photomask and the FEA may be driben at relatively lower voltages.

Abstract translation: 本发明提供一种制造低压驱动场致发射阵列的方法，包括以下步骤：在硅衬底上形成薄的缓冲层，在该层上形成大量氮化硅掩模的图案，氧化衬底的上部和 在氮化物掩模之下的除了氮化物掩模之下的部分之外，在衬底上形成相对较厚的氧化物层，在此期间，厚氧化物层使氮化物掩模的边缘向上移动并在氮化物掩模下方向内延伸，使得氮化物掩模下方的厚氧化物层的边缘 可能有一种鸟的喙形状的横截面，蚀刻掉氮化物掩模图案，通过蚀刻掉薄的缓冲层来暴露由硅酮形状边缘包围的圆形部分的硅衬底，蚀刻暴露的衬底以制造栅极 通过将钙质蒸发器向下蒸发，并在底板和底孔上形成金属层， 垂直于衬底的表面。 与光掩模相比，门孔的直径减小，并且FEA可以在相对较低的电压下进行。

公开(公告)号：US5731597A

公开(公告)日：1998-03-24

申请号：US718876

申请日：1996-09-24

Applicant: Jong Duk Lee ,  Cheon Kyu Lee ,  Dong Hwan Kim

Inventor： Jong Duk Lee ,  Cheon Kyu Lee ,  Dong Hwan Kim

IPC: H01J17/49 ,  H01J1/304 ,  H01L27/00 ,  H01L29/06 ,  H01L29/12

CPC classification number: H01L27/00 ,  H01J1/3042 ,  H01J2201/319

Abstract: The present invention provides field emitter arrays (FEAs) incorporated with metal oxide semiconductor field effect transistors (MOSFETs) and method for fabricating the same which realizes a simultaneous fabrication of two kinds of devices, namely, an FEA and MOSFETs, by using common processing steps among the processes of fabricating Si-FEAs or metal FEAs and MOSFETs, wherein the method comprises steps of forming field emission tips and active regions for MOSFETs by oxidizing selected portions of a silicon nitride layer, forming a gate insulating oxide layer for the FEA and field oxide layers for MOSFETs simultaneously by the LOGOS method and connecting gate electrodes (row line) and cathode electrodes (column line) of the FEA to MOSFETs.

Abstract translation: 本发明提供了结合有金属氧化物半导体场效应晶体管（MOSFET）的场发射极阵列（FEAs）及其制造方法，其通过使用通用的处理步骤实现两种器件即FEA和MOSFET的同时制造 在制造Si-FEAs或金属FEAs和MOSFET的过程中，其中该方法包括以下步骤：通过氧化氮化硅层的选定部分形成用于MOSFET的场致发射尖端和有源区，形成用于FEA的场绝缘氧化物层和场 通过LOGOS方法同时进行MOSFET的氧化物层，并将FEA的栅电极（行线）和阴极电极（列线）连接到MOSFET。

公开(公告)号：US5527200A

公开(公告)日：1996-06-18

申请号：US163818

申请日：1993-12-08

Applicant: Kang-ok Lee ,  Cheon-kyu Lee

Inventor： Kang-ok Lee ,  Cheon-kyu Lee

IPC: H01J1/304 ,  H01J9/02 ,  H01L21/46 ,  H01J9/12

CPC classification number: H01J1/3042 ,  H01J9/025

Abstract: There is disclosed a silicon field emission emitter and a method for making a silicon field emission emitter which has a good electronic characteristic and a simplified making process. The silicon field emission emitter in accordance with the embodiment of the present invention includes a silicon substrate of high density, an insulating layer on the silicon substrate of high density, a cavity formed in the insulating layer, an emitter formed with the silicon substrate of high density in a body in the cavity, and a gate electrode formed on the insulating layer. The insulating layer is made of the thermal oxide film having the thickness of 4000 angstroms and the gate electrode coats the emitter tip.

Abstract translation: 公开了一种硅场致发射体和制造具有良好电子特性和简化制作工艺的硅场致发射体的方法。 根据本发明的实施例的硅场发射发射器包括高密度的硅衬底，高密度的硅衬底上的绝缘层，在绝缘层中形成的腔，形成有高硅衬底的发射极 空腔中的体内的密度，以及形成在绝缘层上的栅电极。 绝缘层由厚度为4000埃的热氧化膜制成，栅电极覆盖发射极尖端。

公开(公告)号：US06326221B1

公开(公告)日：2001-12-04

申请号：US09146597

申请日：1998-09-03

Applicant: Jong Duk Lee ,  Cheon Kyu Lee ,  Hyung Soo Uh

Inventor： Jong Duk Lee ,  Cheon Kyu Lee ,  Hyung Soo Uh

IPC: H01L2100

CPC classification number: H01J9/025

Abstract: The present invention provides methods for manufacturing field emitter arrays on a silicon-on-insulator (SOI) wafer, one of which comprising steps of forming a doped silicon layer by doping a dopant on a single crystalline silicon layer of an SOI wafer; making a buffer oxide layer on the doped silicon layer; making a stripe pattern of silicon nitride on the buffer oxide layer; etching the buffer oxide layer using the stripe pattern as a mask; etching the doped silicon layer anisotropically using the stripe pattern as a mask; making a minute mask pattern of silicon nitride on the buffer oxide layer by patterning the stripe pattern of silicon nitride; selectively oxidizing the upper part of the doped silicon layer to form an oxide layer except on the portions under the mask pattern; etching away the mask pattern of silicon nitride and the buffer oxide layer deposited under the mask pattern; etching away the exposed doped silicon layer for making gate holes of undercut shape; forming metal layers on the SOI wafer and the bottom of the gate holes by evaporating a metallic evaporant downwardly and vertically against the surface of the SOI wafer; and forming the field emitter tips on the metal layer in the gate holes. According to the present invention, electrical isolation between one cathode line and the other may be accomplished without any junction isolation step and an extremely small size of the field emission elements may be formed uniformly over a large area.

Abstract translation: 本发明提供了在绝缘体上硅（SOI）晶片上制造场致发射体阵列的方法，其中之一包括通过在SOI晶片的单晶硅层上掺杂掺杂剂来形成掺杂硅层的步骤; 在掺杂硅层上形成缓冲氧化层; 在缓冲氧化物层上形成氮化硅条纹图案; 使用条纹图案作为掩模蚀刻缓冲氧化物层; 使用条纹图案作为掩模以各向异性蚀刻掺杂硅层; 通过图案化氮化硅的条纹图案，在缓冲氧化物层上形成氮化硅的微小掩模图案; 选择性地氧化掺杂硅层的上部以形成除了掩模图案之下的部分之外的氧化物层; 蚀刻掉掩模图案下沉积的氮化硅和缓冲氧化物层的掩模图案; 蚀刻掉暴露的掺杂硅层以制造底切形状的栅极孔; 通过使金属蒸发器向下和垂直地相对于SOI晶片的表面蒸发，在SOI晶片和栅极孔的底部上形成金属层; 并在栅极孔中的金属层上形成场发射极尖端。 根据本发明，可以在没有任何结隔离步骤的情况下实现一个阴极线与另一个阴极线之间的电隔离，并且可以在大面积上均匀地形成场致发射元件的极小尺寸。