公开(公告)号：US07005349B2

公开(公告)日：2006-02-28

申请号：US10781761

申请日：2004-02-20

申请人： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

发明人： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

摘要： A method of manufacturing a twin-ONO-type SONOS memory using a reverse self-alignment process, wherein an ONO dielectric layer is formed under a gate and physically separated into two portions using a reverse self-alignment process irrespective of photolithographic limits. To facilitate the reverse self-alignment, a buffer layer and spacers for defining the width of the ONO dielectric layer are adopted. Thus, the dispersion of trapped charges during programming and erasing can be appropriately adjusted, thus improving the characteristics of the SONOS. The present invention prevents the redistribution of charges in time after the programming and erasing operations.

摘要翻译： 使用反向自对准工艺制造双ONO型SONOS存储器的方法，其中在栅极下形成ONO电介质层，并且使用反向自对准工艺物理地分离成两部分，而与光刻极限无关。 为了促进反向自对准，采用用于限定ONO介电层宽度的缓冲层和间隔物。 因此，可以适当地调整编程和擦除期间的捕获电荷的分散，从而改善SONOS的特性。 本发明防止在编程和擦除操作之后的时间内重新分配电荷。

公开(公告)号：US5872019A

公开(公告)日：1999-02-16

申请号：US718789

申请日：1996-09-24

申请人： Jong Duk Lee ,  Hyung Soo Uh

发明人： Jong Duk Lee ,  Hyung Soo Uh

IPC分类号： H01J17/49 ,  H01J1/304 ,  H01J9/02 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/00

CPC分类号： H01J9/025 ,  H01J2201/319 ,  H01J2329/00

摘要： The present invention provides field emitter arrays (FEAs) having incorporated with metal oxide semiconductor field effect transistors (MOSFETs) and method for fabricating the same which realizes a simultaneous fabrication of two kinds of devices, namely, the FEA and MOSFETs, by using common processing steps among the processes of fabricating the Si-FEA or the metal FEA and the MOSFETs, wherein the method comprises steps of forming field emission tips and active regions for MOSFETs by oxidizing selected portions of the silicon nitride layer, forming a gate insulating oxide layers for the FEA and field oxide layers for MOSFETs simultaneously by the LOCOS method and connecting gate electrodes(row line) and cathode electrodes(column line) of the FEA to MOSFETs.

摘要翻译： 本发明提供了并入金属氧化物半导体场效应晶体管（MOSFET）的场发射极阵列（FEAs）及其制造方法，其通过使用共同的处理实现两种器件即FEA和MOSFET的同时制造 在制造Si-FEA或金属FEA和MOSFET的过程中的步骤，其中该方法包括以下步骤：通过氧化氮化硅层的选定部分来形成MOSFET的场致发射尖端和有源区，形成用于 通过LOCOS方法同时进行MOSFET的FEA和场氧化物层，并将FEA的栅电极（行线）和阴极（列线）连接到MOSFET。

公开(公告)号：US07439574B2

公开(公告)日：2008-10-21

申请号：US10460673

申请日：2003-06-13

申请人： Chung-woo Kim ,  Byung-gook Park ,  Jong-duk Lee ,  Yong-kyu Lee

发明人： Chung-woo Kim ,  Byung-gook Park ,  Jong-duk Lee ,  Yong-kyu Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7926 ,  G11C11/5628 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7923

摘要： Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on the first insulating layer in a predetermined shape, including source and drain electrodes separated by a predetermined interval; a second insulating layer located on the semiconductor layer between the source and drain electrodes; a memory layer, which is deposited on sides of a portion of the semiconductor layer between the source and drain electrodes and on sides and an upper surface of the second insulating layer, including electron transferring channels and an electron storing layer; and a gate electrode, which is deposited on a surface of the memory layer, for controlling transfer of electrons in the memory layer. The programming method may provide a large capacity, stable, multi-level memory.

摘要翻译： 提供了硅/氧化物/氮化物/氧化物/硅（SONOS）存储器，其制造方法和存储器编程方法。 SONOS存储器包括基板; 堆叠在所述基板上的第一绝缘层; 半导体层，其在预定形状的第一绝缘层上图案化，包括以预定间隔隔开的源极和漏极; 位于源极和漏极之间的半导体层上的第二绝缘层; 存储层，其沉积在源极和漏极之间的半导体层的一部分的侧面上，并且沉积在包括电子传输沟道和电子存储层的第二绝缘层的侧面和上表面上; 以及沉积在存储层的表面上用于控制存储层中电子转移的栅电极。 编程方法可以提供大容量，稳定的多级存储器。

公开(公告)号：US20060086953A1

公开(公告)日：2006-04-27

申请号：US11296397

申请日：2005-12-08

申请人： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

发明人： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

摘要： A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ONO dielectric layer being on the channel region and the drain region, and a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate.

公开(公告)号：US6074887A

公开(公告)日：2000-06-13

申请号：US937527

申请日：1997-09-27

申请人： Jong Duk Lee ,  Donghwan Kim

发明人： Jong Duk Lee ,  Donghwan Kim

IPC分类号： H01J1/30 ,  H01J9/02 ,  H01L27/06 ,  H01L21/00

CPC分类号： H01J9/025 ,  H01L27/0617 ,  H01J2201/319

摘要： The present invention is directed to fabricating a MOSFET-controlled FEA, in which the emitter array and the cathode electrode are separated and connected to each other by a MOSFET, the cathode electrode and the n-well beneath the emitter array thereby being used as a source and a drain of the MOSFET.

摘要翻译： 本发明涉及制造MOSFET控制的FEA，其中发射极阵列和阴极电极通过MOSFET分离并彼此连接，阴极电极和发射极阵列下方的n阱被用作 MOSFET的源极和漏极。

公开(公告)号：US07564084B2

公开(公告)日：2009-07-21

申请号：US11513945

申请日：2006-08-31

申请人： Ki-Whan Song ,  Jong-Duk Lee ,  Byung-Gook Park ,  Hoon Jeong

发明人： Ki-Whan Song ,  Jong-Duk Lee ,  Byung-Gook Park ,  Hoon Jeong

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10802 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/10885 ,  H01L27/10891

摘要： A dynamic random access memory (DRAM) device has dual-gate vertical channel transistors. The device is comprised of pillar-shaped active patterns including source regions contacting with a semiconductor substrate, drain regions formed over the drain regions, and channel regions formed between the source and drain regions. The active patterns are disposed in a cell array field. On the active patterns, bit lines are arranged to connect the drain regions along a direction. Between the active patterns, word lines are arranged intersecting the bit lines. Gat insulation films are interposed between the word lines and active patterns.

摘要翻译： 动态随机存取存储器（DRAM）器件具有双栅极垂直沟道晶体管。 该器件包括柱形有源图案，其包括与半导体衬底接触的源极区域，形成在漏极区域上的漏极区域以及形成在源极和漏极区域之间的沟道区域。 活动图案设置在单元阵列区域中。 在有源图案上，位线布置成沿着一个方向连接漏极区域。 在活动图案之间，字线被布置成与位线相交。 盖子绝缘膜介于字线和有源图案之间。

公开(公告)号：US20070051994A1

公开(公告)日：2007-03-08

申请号：US11513945

申请日：2006-08-31

申请人： Ki-Whan Song ,  Jong-Duk Lee ,  Byung-Gook Park ,  Hoon Jeong

发明人： Ki-Whan Song ,  Jong-Duk Lee ,  Byung-Gook Park ,  Hoon Jeong

IPC分类号： H01L29/94

CPC分类号： H01L27/10802 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/10885 ,  H01L27/10891

摘要： A dynamic random access memory (DRAM) device has dual-gate vertical channel transistors. The device is comprised of pillar-shaped active patterns including source regions contacting with a semiconductor substrate, drain regions formed over the drain regions, and channel regions formed between the source and drain regions. The active patterns are disposed in a cell array field. On the active patterns, bit lines are arranged to connect the drain regions along a direction. Between the active patterns, word lines are arranged intersecting the bit lines. Gat insulation films are interposed between the word lines and active patterns.

摘要翻译： 动态随机存取存储器（DRAM）器件具有双栅极垂直沟道晶体管。 该器件包括柱形有源图案，其包括与半导体衬底接触的源极区域，形成在漏极区域上的漏极区域以及形成在源极和漏极区域之间的沟道区域。 活动图案设置在单元阵列区域中。 在有源图案上，位线布置成沿着一个方向连接漏极区域。 在活动图案之间，字线被布置成与位线相交。 盖子绝缘膜介于字线和有源图案之间。

公开(公告)号：US5885492A

公开(公告)日：1999-03-23

申请号：US6019

申请日：1998-01-12

申请人： Jong Duk Lee ,  Jae Soo Yoo ,  Sung Hee Cho

发明人： Jong Duk Lee ,  Jae Soo Yoo ,  Sung Hee Cho

IPC分类号： C09K11/00 ,  C09K11/62 ,  C09K11/77 ,  B29B9/00

CPC分类号： C09K11/623 ,  C09K11/7703 ,  C09K11/7774 ,  C09K11/7784

摘要： A method for preparing spherical phosphor particles is disclosed, wherein a precursor solution of phosphors is decomposed to solid particles by aerosol pyrolysis and rapid cooling and subsequently the solid particles are heat-treated at a temperature of 1000.degree. C. to 1600.degree. C. for a period of 1 hour to 9 hours.

摘要翻译： 公开了一种制备球形荧光体颗粒的方法，其中通过气溶胶热解和快速冷却将磷光体的前体溶液分解成固体颗粒，随后将固体颗粒在1000℃至1600℃的温度下进行热处理， 时间为1小时至9小时。

公开(公告)号：US5731597A

公开(公告)日：1998-03-24

申请号：US718876

申请日：1996-09-24

申请人： Jong Duk Lee ,  Cheon Kyu Lee ,  Dong Hwan Kim

发明人： Jong Duk Lee ,  Cheon Kyu Lee ,  Dong Hwan Kim

IPC分类号： H01J17/49 ,  H01J1/304 ,  H01L27/00 ,  H01L29/06 ,  H01L29/12

CPC分类号： H01L27/00 ,  H01J1/3042 ,  H01J2201/319

摘要： The present invention provides field emitter arrays (FEAs) incorporated with metal oxide semiconductor field effect transistors (MOSFETs) and method for fabricating the same which realizes a simultaneous fabrication of two kinds of devices, namely, an FEA and MOSFETs, by using common processing steps among the processes of fabricating Si-FEAs or metal FEAs and MOSFETs, wherein the method comprises steps of forming field emission tips and active regions for MOSFETs by oxidizing selected portions of a silicon nitride layer, forming a gate insulating oxide layer for the FEA and field oxide layers for MOSFETs simultaneously by the LOGOS method and connecting gate electrodes (row line) and cathode electrodes (column line) of the FEA to MOSFETs.

摘要翻译： 本发明提供了结合有金属氧化物半导体场效应晶体管（MOSFET）的场发射极阵列（FEAs）及其制造方法，其通过使用通用的处理步骤实现两种器件即FEA和MOSFET的同时制造 在制造Si-FEAs或金属FEAs和MOSFET的过程中，其中该方法包括以下步骤：通过氧化氮化硅层的选定部分形成用于MOSFET的场致发射尖端和有源区，形成用于FEA的场绝缘氧化物层和场 通过LOGOS方法同时进行MOSFET的氧化物层，并将FEA的栅电极（行线）和阴极电极（列线）连接到MOSFET。

公开(公告)号：US07615821B2

公开(公告)日：2009-11-10

申请号：US11346659

申请日：2006-02-03

申请人： Jae Sung Sim ,  Byung Gook Park ,  Jong Duk Lee ,  Chung Woo Kim

发明人： Jae Sung Sim ,  Byung Gook Park ,  Jong Duk Lee ,  Chung Woo Kim

IPC分类号： H01L29/792

CPC分类号： G11C16/0466 ,  G11C16/0483 ,  H01L29/66833 ,  H01L29/792

摘要： The present invention discloses a charge trap flash memory cell with multi-doped layers at the active region, a memory array using of the memory cell, and an operating method of the same. The charge trap memory cell structure of the present invention is characterized by forming multi-doped layers at the active region appropriately, and it is a difference from the conventional art. The present invention induces electrons to band-to-band tunnel at the PN junction with the source/drain region by the multi-doped layers, and accelerates the electrons at the reverse bias to generate an avalanche phenomenon. Therefore, the method for operating a memory array of the present invention comprises programming by injecting holes which are generated by the avalanche phenomenon into multi-dielectric layers of each memory cells, and erasing by injecting electrons through an F-N tunneling from channels into the multi-dielectric layers of each memory cells.

摘要翻译： 本发明公开了一种在有源区域具有多掺杂层的电荷陷阱闪存单元，使用存储单元的存储器阵列及其操作方法。 本发明的电荷陷阱存储单元结构的特征在于在有源区适当地形成多层掺杂层，与现有技术不同。 本发明通过多掺杂层在与源/漏区的PN结处引起电子到带 - 带隧道，并且以反向偏压加速电子以产生雪崩现象。 因此，用于操作本发明的存储器阵列的方法包括通过将由雪崩现象产生的空穴注入到每个存储单元的多个电介质层中来进行编程，以及通过从通道的FN隧道注入电子到多层电介质来擦除， 每个存储单元的电介质层。