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    Planarization method for deep sub micron shallow trench isolation process
    2.
    发明授权
    Planarization method for deep sub micron shallow trench isolation process 失效
    深亚微米浅沟槽隔离工艺的平面化方法

    公开(公告)号：US06774042B1

    公开(公告)日：2004-08-10

    申请号：US10083991

    申请日：2002-02-26

    申请人： Chia-Der Chang ,  Yi-Tung Yen

    发明人： Chia-Der Chang ,  Yi-Tung Yen

    IPC分类号： H01L21302

    CPC分类号： H01L21/31053

    摘要： A method of planarizing wafers using shallow trench isolation is described. The method uses a very hard polishing pad and chemical mechanical polishing with no additional etching required. Trenches are formed in a substrate and filled with a trench dielectric, such as silicon dioxide deposited using high density plasma chemical vapor deposition. A layer of resist is then formed on the layer of trench dielectric. The wafer is then planarized using chemical mechanical polishing and a polishing pad having a hardness of at least Shore “D” 52. The hard polishing pad avoids scratch marks on the trench dielectric, the substrate surface, or any other materials deposited on the substrate surface.

    摘要翻译： 描述了使用浅沟槽隔离来平坦化晶片的方法。 该方法使用非常硬的抛光垫和化学机械抛光，无需额外的蚀刻。 沟槽形成在衬底中并且填充有沟槽电介质，例如使用高密度等离子体化学气相沉积沉积的二氧化硅。 然后在沟槽电介质层上形成一层抗蚀剂。 然后使用化学机械抛光和具有至少肖氏“D”52的硬度的抛光垫将晶片平坦化。硬抛光垫避免沟槽电介质，衬底表面或沉积在衬底表面上的任何其它材料上的划痕 。

    Efficient method for monitoring gate oxide damage related to plasma etch chamber processing history
    3.
    发明授权
    Efficient method for monitoring gate oxide damage related to plasma etch chamber processing history 有权
    用于监测与等离子体蚀刻室处理历史有关的栅极氧化物损伤的高效方法

    公开(公告)号：US6143579A

    公开(公告)日：2000-11-07

    申请号：US298936

    申请日：1999-04-26

    申请人： Chia-Der Chang ,  Chi-Hung Liao ,  Dean-E Lin ,  Sheng-Liang Pan

    发明人： Chia-Der Chang ,  Chi-Hung Liao ,  Dean-E Lin ,  Sheng-Liang Pan

    IPC分类号： H01L21/66 ,  H01L23/544

    CPC分类号： H01L22/34 ,  H01L22/12 ,  H01L2924/0002

    摘要： It has been observed that, when a commercial plasma etcher is used for multiple etching tasks involving a variety of products, the amount of plasma damage incurred depends upon the chamber history of the etching tool. Thus, etching a gate sidewall spacer on a damage sensitive product, for example, in a MOSFET product with very thin gate oxide, may result in significant degradation of the gate oxide if the plasma etching tool had been used to etch vias on another type product in the preceding job. A method for monitoring and recording the chamber history and ascertaining the status of a plasma etching tool with regard to the tendency of said tool to introduce plasma damage in thin gate and tunnel oxide layers is disclosed. The method includes an a oxide damage monitor wafer which contains arrays of simple test devices. The monitor wafers can be partially formed and banked for later use. The test devices comprise a polysilicon plate partially covering a gate oxide. A conformal oxide is formed over the structure and the wafer is subjected to a spacer etch in the plasma etching tool being appraised. Dielectric breakdown the thin oxide is measured and the data is compared to a chamber history of the etcher. Those etching procedures which adversely affect the chamber are identified. Once a chamber history is established, the etcher can be expeditiously scheduled and the incidence of jobs lost to oxide damage greatly reduced.

    摘要翻译： 已经观察到，当商业等离子体蚀刻机用于涉及各种产品的多次蚀刻任务时，所产生的等离子体损伤的量取决于蚀刻工具的腔室历史。 因此，如果已经使用等离子体蚀刻工具蚀刻另一种类型产品上的通孔，则蚀刻损伤敏感产品上的栅极侧壁间隔物（例如，具有非常薄的栅极氧化物的MOSFET产品）可能导致栅极氧化物的显着降解 在前面的工作。 公开了一种用于监测和记录室历史并确定等离子体蚀刻工具关于所述工具在薄栅和隧道氧化物层中引入等离子体损伤的趋势的方法。 该方法包括含有简单测试装置阵列的氧化物损伤监测晶片。 显示器晶片可以部分地形成并分组以供以后使用。 测试装置包括部分覆盖栅极氧化物的多晶硅板。 在结构上形成共形氧化物，并且在评估的等离子体蚀刻工具中对晶片进行间隔蚀刻。 测量介电击穿薄氧化物，并将数据与蚀刻器的室历史进行比较。 识别对腔室有不利影响的蚀刻过程。 一旦建立了房间历史，就可以迅速安排蚀刻器，大大减少对氧化物损失造成的作业的发生。

    Method for forming an improved low power SRAM contact
    4.
    发明授权
    Method for forming an improved low power SRAM contact 失效
    形成改进的低功率SRAM触点的方法

    公开(公告)号：US07714392B2

    公开(公告)日：2010-05-11

    申请号：US11800503

    申请日：2007-05-07

    申请人： Chia-Der Chang ,  Yu-Ching Chang ,  Chien-Chih Chou ,  Yi-Tung Yen

    发明人： Chia-Der Chang ,  Yu-Ching Chang ,  Chien-Chih Chou ,  Yi-Tung Yen

    IPC分类号： H01L23/48

    CPC分类号： H01L21/31116 ,  H01L21/0276 ,  H01L27/11 ,  H01L27/1104

    摘要： A semiconductor device includes a semiconducting substrate having CMOS transistors thereon. A composite etch stop layer including a lowermost silicon oxynitride portion and an uppermost silicon nitride portion is disposed on the semiconducting substrate including the CMOS transistors. At least one dielectric layer is on the composite etch stop layer. A first contact opening extends to a first level through the composite etch stop layer thickness and a second contact opening extends to a second level deeper than the first level through the composite etch stop layer.

    摘要翻译： 半导体器件包括其上具有CMOS晶体管的半导体衬底。 包括最下面的氮氧化硅部分和最上面的氮化硅部分的复合蚀刻停止层设置在包括CMOS晶体管的半导体衬底上。 复合蚀刻停止层上至少有一个介电层。 第一接触开口通过复合蚀刻停止层厚度延伸到第一层，并且第二接触开口通过复合蚀刻停止层延伸到比第一层更深的第二层。

    Method for forming an improved low power SRAM contact
    5.
    发明申请
    Method for forming an improved low power SRAM contact 失效
    形成改进的低功率SRAM触点的方法

    公开(公告)号：US20070205414A1

    公开(公告)日：2007-09-06

    申请号：US11800503

    申请日：2007-05-07

    申请人： Chia-Der Chang ,  Yu-Ching Chang ,  Chien-Chih Chou ,  Yi-Tung Yen

    发明人： Chia-Der Chang ,  Yu-Ching Chang ,  Chien-Chih Chou ,  Yi-Tung Yen

    IPC分类号： H01L27/108

    CPC分类号： H01L21/31116 ,  H01L21/0276 ,  H01L27/11 ,  H01L27/1104

    摘要： A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said BARC layer; and, forming at least a first contact opening exposing said etch stop layer by a first etching process.

    摘要翻译： 一种在半导体器件中形成接触开口的方法，包括提供半导体衬底; 在所述半导体衬底上形成蚀刻停止层; 在所述蚀刻停止层上形成介电层; 在所述介​​电层上形成底部抗反射涂层（BARC）; 在所述BARC层上形成和图案化掩模; 并且形成至少第一接触开口，通过第一蚀刻工艺暴露所述蚀刻停止层。