Abstract:
The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders.
Abstract:
A method and device are provided for adjusting brightness of an optical touch panel. The optical touch panel comprises a microprocessor, a display module including a back light source, and an optical position detection device including optical transmitting devices and optical receiving devices. The method comprises detecting, via the optical receiving devices, a current ambient light level on the display module. The method further comprises generating, via the optical receiving devices, a current ambient light level signal indicative of the current ambient light level and transmitting the current ambient light level signal to the microprocessor. Furthermore, the method comprises adjusting, via the microprocessor, brightness of the back light source based on the current ambient light level signal.
Abstract:
Apparatus, systems, and methods for data movement in a memory device are described. In one embodiment, a memory controller comprises logic to move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface. Other embodiments are also disclosed and claimed.
Abstract:
A method and device are provided for adjusting brightness of an optical touch panel. The optical touch panel comprises a microprocessor, a display module including a back light source, and an optical position detection device including optical transmitting devices and optical receiving devices. The method comprises detecting, via the optical receiving devices, a current ambient light level on the display module. The method further comprises generating, via the optical receiving devices, a current ambient light level signal indicative of the current ambient light level and transmitting the current ambient light level signal to the microprocessor. Furthermore, the method comprises adjusting, via the microprocessor, brightness of the back light source based on the current ambient light level signal.
Abstract:
An SRAM memory cell that has a relatively small power consumption when writing a write value of ‘0’ to the memory cell includes cross-coupled first and second inverters, at least one read access transistor for selectively coupling a respective read bit line to a common connection node of a respective one of the first and second inverters, a switching transistor for selectively coupling the second inverter to a ground terminal, and a write access transistor for selectively coupling the common connection node of the second inverter to a write bit line.
Abstract:
The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders.
Abstract:
An SRAM memory cell that has a relatively small power consumption when writing a write value of ‘0’ to the memory cell includes cross-coupled first and second inverters, at least one read access transistor for selectively coupling a respective read bit line to a common connection node of a respective one of the first and second inverters, a switching transistor for selectively coupling the second inverter to a ground terminal, and a write access transistor for selectively coupling the common connection node of the second inverter to a write bit line.