公开(公告)号：US07634752B2

公开(公告)日：2009-12-15

申请号：US11592734

申请日：2006-11-03

申请人： Mikhail Iotov ,  Greg Starr

发明人： Mikhail Iotov ,  Greg Starr

IPC分类号： G06F17/50

CPC分类号： H03K19/17732 ,  G11C27/00 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/183

摘要： A system and method facilitates the implementation of analog circuitry in electronic programmable devices. A user can specify user measurable parameters for analog features of the circuit, without requiring knowledge of the internal way in which those analog circuit are implemented in the programmable device to achieve desired properties of the analog parameters of interest. The implementation can be performed in different devices which may implement the analog circuit in vastly different ways.

摘要翻译： 一种系统和方法有助于在电子可编程器件中实现模拟电路。 用户可以为电路的模拟特征指定用户可测量的参数，而不需要知道在可编程设备中实现那些模拟电路的内部方式以获得感兴趣的模拟参数的所需属性。 该实现可以在可以以非常不同的方式实现模拟电路的不同设备中执行。

公开(公告)号：US07046048B2

公开(公告)日：2006-05-16

申请号：US10915201

申请日：2004-08-09

申请人： Greg Starr ,  Edward Aung

发明人： Greg Starr ,  Edward Aung

IPC分类号： H03K17/00

CPC分类号： G06F11/1604 ,  G06F1/08 ,  G06F11/20 ,  H03L7/095 ,  H03L7/143 ,  H04L7/0008 ,  H04L7/0083

摘要： In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

公开(公告)号：US20050088867A1

公开(公告)日：2005-04-28

申请号：US10353816

申请日：2003-01-28

申请人： Mihail Iotov ,  Greg Starr

发明人： Mihail Iotov ,  Greg Starr

IPC分类号： G11C27/00 ,  H03K19/177 ,  H03L7/089 ,  H03L7/093 ,  H03L7/183

CPC分类号： H03K19/17732 ,  G11C27/00 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/183

摘要： A system and method facilitates the implementation of analog circuitry in electronic programmable devices. A user can specify user measurable parameters for analog features of the circuit, without requiring knowledge of the internal way in which those analog circuit are implemented in the programmable device to achieve desired properties of the analog parameters of interest. The implementation can be performed in different devices which may implement the analog circuit in vastly different ways.

摘要翻译： 一种系统和方法有助于在电子可编程器件中实现模拟电路。 用户可以为电路的模拟特征指定用户可测量的参数，而不需要知道在可编程设备中实现那些模拟电路的内部方式以获得感兴趣的模拟参数的所需属性。 该实现可以在可以以非常不同的方式实现模拟电路的不同设备中执行。

公开(公告)号：US20050017775A1

公开(公告)日：2005-01-27

申请号：US10921453

申请日：2004-08-18

申请人： Greg Starr

发明人： Greg Starr

IPC分类号： H03L7/081 ,  H03L7/089 ,  H03L7/18 ,  H03L7/06

CPC分类号： H03L7/18 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0893

摘要： An integrated circuit including a phase lock loop or delay lock loop) (PLL/DLL) Circuit comprising: a clock input terminal for accepting a clock signal; a phase/frequency detector (PFD) circuit including a reference clock input connected to the clock input terminal and including a PFD feedback input and including a PFD output; a charge pump (CP) circuit; at least one external feedforward output terminal; a loop filter (LF); a loop controlled signal source (LCSS); and a feedback circuit connected between a LCSS output and the PFD feedback input, the feedback circuit including, an external feedback input terminal; first frequency selection circuitry to produce a first programmable feedback signal; second frequency selection circuitry to produce a second feedback signal; and multiplex circuitry connected with the LCSS output, the external feedback input terminal and the first and second frequency selection circuitry, to cause either the first programmable feedback signal or the second programmable feedback signal to be coupled to the PFD feedback input.

摘要翻译： 一种包括锁相环或延迟锁环的集成电路（PLL / DLL）电路，包括：用于接收时钟信号的时钟输入端; 相位/频率检测器（PFD）电路，包括连接到时钟输入端的参考时钟输入，并包括PFD反馈输入并包括PFD输出; 电荷泵（CP）电路; 至少一个外部前馈输出端子; 环路滤波器（LF）; 环路控制信号源（LCSS）; 以及连接在LCSS输出和PFD反馈输入之间的反馈电路，所述反馈电路包括外部反馈输入端子; 第一频率选择电路，用于产生第一可编程反馈信号; 第二频率选择电路以产生第二反馈信号; 以及与LCSS输出端连接的复用电路，外部反馈输入端和第一和第二频率选择电路，以使第一可编程反馈信号或第二可编程反馈信号耦合到PFD反馈输入。

公开(公告)号：US07660841B2

公开(公告)日：2010-02-09

申请号：US10783789

申请日：2004-02-20

申请人： Leon Zheng ,  Martin Langhammer ,  Nitin Prasad ,  Greg Starr ,  Chiao Kai Hwang ,  Kumara Tharmalingam

发明人： Leon Zheng ,  Martin Langhammer ,  Nitin Prasad ,  Greg Starr ,  Chiao Kai Hwang ,  Kumara Tharmalingam

IPC分类号： G06F7/38

CPC分类号： G06F7/5443 ,  G06F2207/3884

摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.

摘要翻译： 乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。 当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。 为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。 或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

公开(公告)号：US20060197558A1

公开(公告)日：2006-09-07

申请号：US11398384

申请日：2006-04-04

申请人： Greg Starr ,  Edward Aung

发明人： Greg Starr ,  Edward Aung

IPC分类号： G06F1/08

CPC分类号： G06F11/1604 ,  G06F1/08 ,  G06F11/20 ,  H03L7/095 ,  H03L7/143 ,  H04L7/0008 ,  H04L7/0083

摘要： In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

公开(公告)号：US06891401B2

公开(公告)日：2005-05-10

申请号：US10213115

申请日：2002-08-05

申请人： Greg Starr ,  Edward Aung

发明人： Greg Starr ,  Edward Aung

IPC分类号： G06F1/04 ,  G06F1/08 ,  H03K5/00 ,  H03K5/19 ,  H03K17/00 ,  H03L7/00 ,  H03L7/095 ,  H03L7/14 ,  H04L7/00 ,  G01R19/00

CPC分类号： G06F11/1604 ,  G06F1/08 ,  G06F11/20 ,  H03L7/095 ,  H03L7/143 ,  H04L7/0008 ,  H04L7/0083

摘要： In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

摘要翻译： 在一个方面，一个实施例提供了一种时钟损耗检测和切换电路和方法，其中时钟切换响应主信号的丢失和附加的开关命令信令。 在另一方面，一个实施例提供了利用计数器和复位信号比较主时钟和次时钟信号的时钟损耗检测电路和方法。

公开(公告)号：US06812756B2

公开(公告)日：2004-11-02

申请号：US10669295

申请日：2003-09-23

申请人： Greg Starr

发明人： Greg Starr

IPC分类号： H03L706

CPC分类号： H03L7/18 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0893

摘要： An integrated circuit including a phase lock loop or delay lock loop (PLL/DLL) circuit comprising: a clock input terminal for accepting a clock signal; a phase/frequency detector (PFD) circuit including a reference clock input connected to the clock input terminal and including a PFD feedback input and including a PFD output; a charge pump (CP) circuit; at least one external feedforward output terminal; a loop filter (LF); a loop controlled signal source (LCSS); and a feedback circuit connected between a LCSS output and the PFD feedback input, the feedback circuit including, an external feedback input terminal; first frequency selection circuitry to produce a first programmable feedback signal; second frequency selection circuitry to produce a second feedback signal; and multiplex circuitry connected with the LCSS output, the external feedback input terminal and the first and second frequency selection circuitry, to cause either the first programmable feedback signal or the second programmable feedback signal to be coupled to the PFD feedback input.

摘要翻译： 一种包括锁相环或延迟锁定环（PLL / DLL）电路的集成电路，包括：用于接收时钟信号的时钟输入端; 相位/频率检测器（PFD）电路，包括连接到时钟输入端的参考时钟输入，并包括PFD反馈输入并包括PFD输出; 电荷泵（CP）电路; 至少一个外部前馈输出端子; 环路滤波器（LF）; 环路控制信号源（LCSS）; 以及连接在LCSS输出和PFD反馈输入之间的反馈电路，所述反馈电路包括外部反馈输入端子; 第一频率选择电路，用于产生第一可编程反馈信号; 第二频率选择电路以产生第二反馈信号; 以及与LCSS输出端连接的复用电路，外部反馈输入端和第一和第二频率选择电路，以使第一可编程反馈信号或第二可编程反馈信号耦合到PFD反馈输入。

公开(公告)号：US06633185B2

公开(公告)日：2003-10-14

申请号：US10137802

申请日：2002-05-01

申请人： Greg Starr

发明人： Greg Starr

IPC分类号： H03L706

CPC分类号： H03L7/18 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0893

摘要： An integrated circuit including a phase lock loop or delay lock loop (PLL/DLL) circuit comprising: a clock input terminal for accepting a clock signal; a phase/frequency detector (PFD) circuit including a reference clock input connected to the clock input terminal and including a PFD feedback input and including a PFD output; a charge pump (CP) circuit; at least one external feedforward output terminal; a loop filter (LF); a loop controlled signal source (LCSS); and a feedback circuit connected between a LCSS output and the PFD feedback input, the feedback circuit including, an external feedback input terminal; first frequency selection circuitry to produce a first programmable feedback signal; second frequency selection circuitry to produce a second feedback signal; and multiplex circuitry connected with the LCSS output, the external feedback input terminal and the first and second frequency selection circuitry, to cause either the first programmable feedback signal or the second programmable feedback signal to be coupled to the PFD feedback input.

摘要翻译： 一种包括锁相环或延迟锁定环（PLL / DLL）电路的集成电路，包括：用于接收时钟信号的时钟输入端; 相位/频率检测器（PFD）电路，包括连接到时钟输入端的参考时钟输入，并包括PFD反馈输入并包括PFD输出; 电荷泵（CP）电路; 至少一个外部前馈输出端子; 环路滤波器（LF）; 环路控制信号源（LCSS）; 以及连接在LCSS输出和PFD反馈输入之间的反馈电路，所述反馈电路包括外部反馈输入端子; 第一频率选择电路，用于产生第一可编程反馈信号; 第二频率选择电路以产生第二反馈信号; 以及与LCSS输出端连接的多路复用电路，外部反馈输入端和第一和第二频率选择电路，以使第一可编程反馈信号或第二可编程反馈信号耦合到PFD反馈输入端。

公开(公告)号：US07023251B2

公开(公告)日：2006-04-04

申请号：US10921453

申请日：2004-08-18

申请人： Greg Starr

发明人： Greg Starr

IPC分类号： H03L7/06

CPC分类号： H03L7/18 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0893

摘要： An integrated circuit including a phase lock loop or delay lock loop) (PLL/DLL) circuit comprising: a clock input terminal for accepting a clock signal; a phase/frequency detector (PFD) circuit including a reference clock input connected to the clock input terminal and including a PFD feedback input and including a PFD output; a charge pump (CP) circuit; at least one external feedforward output terminal; a loop filter (LF); a loop controlled signal source (LCSS); and a feedback circuit connected between a LCSS output and the PFD feedback input, the feedback circuit including, an external feedback input terminal; first frequency selection circuitry to produce a first programmable feedback signal; second frequency selection circuitry to produce a second feedback signal; and multiplex circuitry connected with the LCSS output, the external feedback input terminal and the first and second frequency selection circuitry, to cause either the first programmable feedback signal or the second programmable feedback signal to be coupled to the PFD feedback input.

摘要翻译： 一种包括锁相环或延迟锁环的集成电路（PLL / DLL）电路，包括：用于接收时钟信号的时钟输入端; 相位/频率检测器（PFD）电路，包括连接到时钟输入端的参考时钟输入，并包括PFD反馈输入并包括PFD输出; 电荷泵（CP）电路; 至少一个外部前馈输出端子; 环路滤波器（LF）; 环路控制信号源（LCSS）; 以及连接在LCSS输出和PFD反馈输入之间的反馈电路，所述反馈电路包括外部反馈输入端子; 第一频率选择电路，用于产生第一可编程反馈信号; 第二频率选择电路以产生第二反馈信号; 以及与LCSS输出端连接的复用电路，外部反馈输入端和第一和第二频率选择电路，以使第一可编程反馈信号或第二可编程反馈信号耦合到PFD反馈输入。