利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.016 秒)

    METHOD AND STRUCTURE FOR DISSIPATING HEAT AWAY FROM A RESISTOR HAVING NEIGHBORING DEVICES AND INTERCONNECTS
    1.
    发明申请
    METHOD AND STRUCTURE FOR DISSIPATING HEAT AWAY FROM A RESISTOR HAVING NEIGHBORING DEVICES AND INTERCONNECTS 有权
    用于从具有相邻设备和互连的电阻器散热的方法和结构

    公开(公告)号：US20120002375A1

    公开(公告)日：2012-01-05

    申请号：US12827742

    申请日：2010-06-30

    申请人： Jian-Hong LIN ,  Chin Chuan PENG ,  Tzu-Li LEE ,  Bi-Ling LIN ,  Bor-Jou WEI ,  Chien Shih TSAI

    发明人： Jian-Hong LIN ,  Chin Chuan PENG ,  Tzu-Li LEE ,  Bi-Ling LIN ,  Bor-Jou WEI ,  Chien Shih TSAI

    IPC分类号： H05K7/20 ,  H01L21/02

    CPC分类号： H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.

    摘要翻译： 一种半导体结构，用于从具有相邻器件和互连的电阻器散热。 半导体结构包括半导体衬底，设置在半导体衬底之上的电阻器和设置在电阻器上方的热保护结构。 热保护结构具有多个散热元件，散热元件的一端设置成与热保护结构导热接触，另一端与半导体衬底导热接触。 热保护结构接收从电阻器产生的热量，并且散热元件将热量散发到半导体衬底。

    Method for determining electro-migration failure mode
    4.
    发明授权
    Method for determining electro-migration failure mode 有权
    确定电迁移故障模式的方法

    公开(公告)号：US07449911B2

    公开(公告)日：2008-11-11

    申请号：US11729759

    申请日：2007-03-29

    申请人： Yi-Lung Cheng ,  Bi-Ling Liu ,  Chin-Chuang Peng ,  Chien-Shih Tsai ,  Hway-Chi Lin

    发明人： Yi-Lung Cheng ,  Bi-Ling Liu ,  Chin-Chuang Peng ,  Chien-Shih Tsai ,  Hway-Chi Lin

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2858

    摘要： A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.

    摘要翻译： 一种用于测试集成电路的方法包括形成多个基本上相同的第一测试结构，每个第一测试结构包括连接到第一金属线的第一通孔结构，测试多个第一测试结构以获得第一多个故障时间，以及形成 多个基本上相同的第二测试结构，每个包括连接到第二金属线的第二通孔结构，其中第二通孔结构具有与第一通孔结构基本上不同的可靠性，并且其中第一金属线和第二金属线基本相同 相同。 该方法还包括对多个第二测试结构进行压力测试以获得第二多个故障时间，以及确定多个第一测试结构和多个第二测试结构的早期故障。