公开(公告)号：US08848374B2

公开(公告)日：2014-09-30

申请号：US12827742

申请日：2010-06-30

申请人： Jian-Hong Lin ,  Chin Chuan Peng ,  Tzu-Li Lee ,  Bi-Ling Lin ,  Bor-Jou Wei ,  Chien Shih Tsai

发明人： Jian-Hong Lin ,  Chin Chuan Peng ,  Tzu-Li Lee ,  Bi-Ling Lin ,  Bor-Jou Wei ,  Chien Shih Tsai

IPC分类号： H05K7/20 ,  H01L49/02 ,  H01L23/522 ,  H01L23/367

CPC分类号： H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.

摘要翻译： 一种半导体结构，用于从具有相邻器件和互连的电阻器散热。 半导体结构包括半导体衬底，设置在半导体衬底之上的电阻器和设置在电阻器上方的热保护结构。 热保护结构具有多个散热元件，散热元件的一端设置成与热保护结构导热接触，另一端与半导体衬底导热接触。 热保护结构接收从电阻器产生的热量，并且散热元件将热量散发到半导体衬底。

公开(公告)号：US20090058434A1

公开(公告)日：2009-03-05

申请号：US11849836

申请日：2007-09-04

申请人： Jian-Hong Lin ,  Chin Chuan Peng ,  Shou-Chung Lee ,  Chien-Jung Wang ,  Chien Shih Tsai ,  Bi-Ling Lin ,  Yi-Lung Cheng

发明人： Jian-Hong Lin ,  Chin Chuan Peng ,  Shou-Chung Lee ,  Chien-Jung Wang ,  Chien Shih Tsai ,  Bi-Ling Lin ,  Yi-Lung Cheng

IPC分类号： G01R27/00

CPC分类号： G01R31/2858 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.

摘要翻译： 提供了一种用于测量互连性质的方法。 该方法包括以下步骤。 提供多个互连测试图案。 形成多个互连测试图案并联连接的焊盘。 至少一个电阻器形成在所述多个互连测试图案中的至少一个与所述焊盘之间。 通过对焊盘施加电流，电压和/或机械应力来测量多个互连测试图案的性质。

公开(公告)号：US07646207B2

公开(公告)日：2010-01-12

申请号：US11849836

申请日：2007-09-04

申请人： Jian-Hong Lin ,  Chin Chuan Peng ,  Shou-Chung Lee ,  Chien-Jung Wang ,  Chien Shih Tsai ,  Bi-Ling Lin ,  Yi-Lung Cheng

发明人： Jian-Hong Lin ,  Chin Chuan Peng ,  Shou-Chung Lee ,  Chien-Jung Wang ,  Chien Shih Tsai ,  Bi-Ling Lin ,  Yi-Lung Cheng

IPC分类号： G01R27/08

CPC分类号： G01R31/2858 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.

摘要翻译： 提供了一种用于测量互连性质的方法。 该方法包括以下步骤。 提供多个互连测试图案。 形成多个互连测试图案并联连接的焊盘。 至少一个电阻器形成在所述多个互连测试图案中的至少一个与所述焊盘之间。 通过对焊盘施加电流，电压和/或机械应力来测量多个互连测试图案的性质。

公开(公告)号：US20130063175A1

公开(公告)日：2013-03-14

申请号：US13231812

申请日：2011-09-13

申请人： Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

发明人： Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

IPC分类号： G01R31/26 ,  H01L23/538 ,  H01L23/522

CPC分类号： H01L23/5256 ,  G01R31/2853 ,  G01R31/2858 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

摘要翻译： 公开了半导体器件组件和方法。 在一个实施例中，半导体器件部件包括具有第一表面，与第一表面相对的第二表面，第一端和与第一端相对的第二端的导电段。 第一通孔在第一端耦合到导电段的第二表面。 第二通孔在第二端处耦合到导电段的第一表面，并且第三通孔在第二端耦合到导电段的第二表面。

公开(公告)号：US08648592B2

公开(公告)日：2014-02-11

申请号：US13231812

申请日：2011-09-13

申请人： Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

发明人： Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

IPC分类号： G01V3/00

CPC分类号： H01L23/5256 ,  G01R31/2853 ,  G01R31/2858 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

摘要翻译： 公开了半导体器件组件和方法。 在一个实施例中，半导体器件部件包括具有第一表面，与第一表面相对的第二表面，第一端和与第一端相对的第二端的导电段。 第一通孔在第一端耦合到导电段的第二表面。 第二通孔在第二端处耦合到导电段的第一表面，并且第三通孔在第二端耦合到导电段的第二表面。

公开(公告)号：US20100327456A1

公开(公告)日：2010-12-30

申请号：US12879770

申请日：2010-09-10

申请人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

发明人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

IPC分类号： H01L23/52

CPC分类号： H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

摘要： An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

摘要翻译： 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

公开(公告)号：US07816256B2

公开(公告)日：2010-10-19

申请号：US11487741

申请日：2006-07-17

申请人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

发明人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

摘要： An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

摘要翻译： 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

公开(公告)号：US20080014741A1

公开(公告)日：2008-01-17

申请号：US11487741

申请日：2006-07-17

申请人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

发明人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

摘要： An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

摘要翻译： 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

公开(公告)号：US20070018279A1

公开(公告)日：2007-01-25

申请号：US11186581

申请日：2005-07-21

申请人： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

发明人： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC分类号： H01L29/00

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

摘要翻译： 半导体结构防止用于熔断保险丝的能量造成损坏。 半导体结构包括器件，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US08242576B2

公开(公告)日：2012-08-14

申请号：US11186581

申请日：2005-07-21

申请人： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

发明人： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC分类号： H01L23/52

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

摘要翻译： 半导体结构防止用于熔断保险丝的能量造成损坏。 半导体结构包括器件，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。