公开(公告)号：US08258827B2

公开(公告)日：2012-09-04

申请号：US12789424

申请日：2010-05-27

申请人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B19/00

CPC分类号： H03B19/14

摘要： A frequency doubler receiving an in-phase oscillating signal and an inverse oscillating signal and generating an output signal oscillating at a multiplied frequency, accordingly. The frequency doubler has a first transistor, a second transistor, a first inductor and a second inductor. A first terminal of the first transistor and a first terminal of the second transistor are at a common voltage. The frequency doubler receives the in-phase oscillating signal and the inverse oscillating signal via control terminals of the first and second transistors. The first and second inductors couple a second terminal of the first transistor and a second terminal of the second transistor to an output terminal of the frequency doubler, respectively. The first and second inductors may be separate inductance devices or, in another case, be implemented by a symmetric inductor.

摘要翻译： 接收同相振荡信号的倍频器和反相振荡信号，并相应地产生以倍频振荡的输出信号。 倍频器具有第一晶体管，第二晶体管，第一电感器和第二电感器。 第一晶体管的第一端子和第二晶体管的第一端子处于公共电压。 倍频器通过第一和第二晶体管的控制端接收同相振荡信号和反相振荡信号。 第一和第二电感分别将第一晶体管的第二端子和第二晶体管的第二端子耦合到倍频器的输出端子。 第一和第二电感器可以是分离的电感器件，或者在另一种情况下可由对称电感器来实现。

公开(公告)号：US08035457B2

公开(公告)日：2011-10-11

申请号：US12687891

申请日：2010-01-15

申请人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B5/08

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1225 ,  H03B5/1253 ,  H03B5/1271 ,  H03B5/1296

摘要： A voltage controlled oscillator (VCO) includes a voltage controlled current source (VCCS), a negative resistance circuit (NRC), a first transformer, a second transformer, a first transistor and a second transistor. A current terminal of the VCCS receives a control voltage. First terminals of first and second current paths in the NRC are coupled to a current terminal of the VCCS. Primary sides of the first and the second transformers are respectively coupled to second terminals of the first and the second current paths. Secondary sides of the first and the second transformers are first and second output terminals of the VCO, respectively. First terminals of the first and the second transistor are respectively coupled to the secondary sides of the first and the second transformers. Control terminals of the first and the second transformers are respectively coupled to the primary sides of the first and the second transformers.

摘要翻译： 压控振荡器（VCO）包括压控电流源（VCCS），负电阻电路（NRC），第一变压器，第二变压器，第一晶体管和第二晶体管。 VCCS的电流端子接收控制电压。 NRC中的第一和第二电流路径的第一端子耦合到VCCS的电流端子。 第一和第二变压器的主侧分别耦合到第一和第二电流路径的第二端。 第一和第二变压器的次级侧分别是VCO的第一和第二输出端。 第一和第二晶体管的第一端分别耦合到第一和第二变压器的次级侧。 第一变压器和第二变压器的控制端子分别与第一变压器和第二变压器的一次侧接合。

公开(公告)号：US20110175651A1

公开(公告)日：2011-07-21

申请号：US12789424

申请日：2010-05-27

申请人： Chih-Hsiang CHANG ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang CHANG ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B19/06 ,  H03B19/00

CPC分类号： H03B19/14

摘要： A frequency doubler receiving an in-phase oscillating signal and an inverse oscillating signal and generating an output signal oscillating at a multiplied frequency, accordingly. The frequency doubler has a first transistor, a second transistor, a first inductor and a second inductor. A first terminal of the first transistor and a first terminal of the second transistor are at a common voltage. The frequency doubler receives the in-phase oscillating signal and the inverse oscillating signal via control terminals of the first and second transistors. The first and second inductors couple a second terminal of the first transistor and a second terminal of the second transistor to an output terminal of the frequency doubler, respectively. The first and second inductors may be separate inductance devices or, in another case, be implemented by a symmetric inductor.

摘要翻译： 接收同相振荡信号的倍频器和反相振荡信号，并相应地产生以倍频振荡的输出信号。 倍频器具有第一晶体管，第二晶体管，第一电感器和第二电感器。 第一晶体管的第一端子和第二晶体管的第一端子处于公共电压。 倍频器通过第一和第二晶体管的控制端接收同相振荡信号和反相振荡信号。 第一和第二电感分别将第一晶体管的第二端子和第二晶体管的第二端子耦合到倍频器的输出端子。 第一和第二电感器可以是分离的电感器件，或者在另一种情况下可由对称电感器来实现。

公开(公告)号：US20110018645A1

公开(公告)日：2011-01-27

申请号：US12687891

申请日：2010-01-15

申请人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B7/00 ,  H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1225 ,  H03B5/1253 ,  H03B5/1271 ,  H03B5/1296

摘要： A voltage controlled oscillator (VCO) includes a voltage controlled current source (VCCS), a negative resistance circuit (NRC), a first transformer, a second transformer, a first transistor and a second transistor. A current terminal of the VCCS receives a control voltage. First terminals of first and second current paths in the NRC are coupled to a current terminal of the VCCS. Primary sides of the first and the second transformers are respectively coupled to second terminals of the first and the second current paths. Secondary sides of the first and the second transformers are first and second output terminals of the VCO, respectively. First terminals of the first and the second transistor are respectively coupled to the secondary sides of the first and the second transformers. Control terminals of the first and the second transformers are respectively coupled to the primary sides of the first and the second transformers.

摘要翻译： 压控振荡器（VCO）包括压控电流源（VCCS），负电阻电路（NRC），第一变压器，第二变压器，第一晶体管和第二晶体管。 VCCS的电流端子接收控制电压。 NRC中的第一和第二电流路径的第一端子耦合到VCCS的电流端子。 第一和第二变压器的主侧分别耦合到第一和第二电流路径的第二端。 第一和第二变压器的次级侧分别是VCO的第一和第二输出端。 第一和第二晶体管的第一端分别耦合到第一和第二变压器的次级侧。 第一变压器和第二变压器的控制端子分别与第一变压器和第二变压器的一次侧接合。

公开(公告)号：US20120154060A1

公开(公告)日：2012-06-21

申请号：US13018378

申请日：2011-01-31

申请人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1243 ,  H03B27/00

摘要： A quadrature voltage-controlled oscillator (QVCO) apparatus including a first VCO, a second VCO, a first energy-storage element, a second energy-storage element, a third energy-storage element and a fourth energy-storage element is provided. The first VCO has a first and a second phase output ends. The second VCO has a third and a fourth phase output ends. A first and a second ends of the first energy-storage element respectively connect to the first and the third phase output ends. A first and a second ends of the second energy-storage element respectively connect to the second and the third phase output ends. A first and a second ends of the third energy-storage element respectively connect to the second and the fourth phase output ends. A first and a second ends of the fourth energy-storage element respectively connect to the first and the fourth phase output ends.

摘要翻译： 提供了包括第一VCO，第二VCO，第一能量存储元件，第二能量存储元件，第三能量存储元件和第四能量存储元件的正交压控振荡器（QVCO）装置。 第一个VCO具有第一和第二相输出端。 第二个VCO具有第三和第四相输出端。 第一能量存储元件的第一端和第二端分别连接到第一和第三相输出端。 第二能量存储元件的第一端和第二端分别连接到第二和第三相输出端。 第三储能元件的第一和第二端分别连接到第二和第四相输出端。 第四能量存储元件的第一和第二端分别连接到第一和第四相输出端。

公开(公告)号：US08238501B2

公开(公告)日：2012-08-07

申请号：US12266530

申请日：2008-11-06

申请人： Ching Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

发明人： Ching Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

IPC分类号： H04L7/033

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0041 ,  H04L7/0087 ,  H04Q11/0067 ,  H04Q2011/0079

摘要： A burst-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase.

摘要翻译： 提供了使用相位选择技术的突发模式时钟和数据恢复电路。 在数据恢复电路中，使用锁相环（PLL）电路来提供多个具有时钟相位的固定时钟信号。 过采样相位选择电路耦合到锁相环电路，用于通过使用时钟信号检测接收数据信号的数据沿，并根据数据沿的位置选择要锁定的时钟相位。 延迟锁定回路（DLL）电路耦合到锁相环电路和过采样相位选择电路，并用于将数据信号的数据相位与所选择的时钟信号的时钟相位进行比较，以便延迟 数据信号的数据相位延迟一个延迟时间，直到数据相位被锁定为时钟相位。

公开(公告)号：US20100040182A1

公开(公告)日：2010-02-18

申请号：US12266530

申请日：2008-11-06

申请人： Ching-Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

发明人： Ching-Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0041 ,  H04L7/0087 ,  H04Q11/0067 ,  H04Q2011/0079

摘要： A bust-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase.

摘要翻译： 提供了采用相位选择技术的突发模式时钟和数据恢复电路。 在数据恢复电路中，使用锁相环（PLL）电路来提供多个具有时钟相位的固定时钟信号。 过采样相位选择电路耦合到锁相环电路，用于通过使用时钟信号检测接收数据信号的数据沿，并根据数据沿的位置选择要锁定的时钟相位。 延迟锁定回路（DLL）电路耦合到锁相环电路和过采样相位选择电路，并用于将数据信号的数据相位与所选择的时钟信号的时钟相位进行比较，以便延迟 数据信号的数据相位延迟一个延迟时间，直到数据相位被锁定为时钟相位。

公开(公告)号：US20100261467A1

公开(公告)日：2010-10-14

申请号：US12683897

申请日：2010-01-07

申请人： Chie-Ming CHOU ,  Jung-Mao Lin

发明人： Chie-Ming CHOU ,  Jung-Mao Lin

IPC分类号： H04W4/00

CPC分类号： H04W24/02 ,  H04W52/244 ,  H04W52/247 ,  H04W52/386 ,  H04W52/40 ,  H04W84/045

摘要： A base station includes an interface for providing communication with at least one other base station and communication with a network server in a communication system, a processor coupled to the interface, and a memory coupled to the processor. The memory stores program instructions executable by the processor to connect to the network server using the interface, send information to the network server regarding femtocell capability, configure operating parameters of the base station based on the information, including to configure transmission power of the base station, and operate the base station based on the operating parameters.

摘要翻译： 基站包括用于提供与至少一个其他基站的通信并与通信系统中的网络服务器进行通信的接口，耦合到该接口的处理器以及耦合到该处理器的存储器。 存储器存储可由处理器执行的程序指令，以使用接口连接到网络服务器，基于该信息向网络服务器发送关于毫微微小区能力的信息，配置基站的操作参数，包括配置基站的传输功率 ，并且基于操作参数操作基站。

公开(公告)号：US20120082103A1

公开(公告)日：2012-04-05

申请号：US13196911

申请日：2011-08-03

申请人： Jung-Mao Lin ,  Chie-Ming Chou

发明人： Jung-Mao Lin ,  Chie-Ming Chou

IPC分类号： H04W74/08 ,  H04W88/02 ,  H04W72/00

CPC分类号： H04W74/085 ,  H04W48/02

摘要： A random access method, a parameter assignment method, a wireless communication device, and a base station using the same are provided. The random access method is adapted for the wireless communication device to perform a random access process with the base station, and includes following steps. The wireless communication device transmits a preamble code to the base station, obtains an indicator in a packet transmitted from the base station, and determines whether to obtain a first random access response and a second random access response according to the indicator. When the transmission of the preamble code by the wireless communication device encounters a collision and the indicator is set the wireless communication device performs a random access process by using the command in the first random access response. Otherwise, the wireless communication device performs the conventional process.

摘要翻译： 提供了一种随机存取方法，参数分配方法，无线通信装置和使用该方法的基站。 随机接入方法适用于无线通信设备与基站进行随机接入过程，并且包括以下步骤。 无线通信装置向基站发送前导码，获取从基站发送的分组中的指示符，并根据该指标确定是否获得第一随机接入响应和第二随机接入响应。 当由无线通信设备发送前导码遇到冲突时，无线通信设备通过使用第一随机接入响应中的命令来执行随机接入过程。 否则，无线通信装置执行常规处理。

公开(公告)号：US08588163B2

公开(公告)日：2013-11-19

申请号：US13196911

申请日：2011-08-03

申请人： Jung-Mao Lin ,  Chie-Ming Chou

发明人： Jung-Mao Lin ,  Chie-Ming Chou

IPC分类号： H04W4/00

CPC分类号： H04W74/085 ,  H04W48/02

摘要： A random access method, a parameter assignment method, a wireless communication device, and a base station using the same are provided. The random access method is adapted for the wireless communication device to perform a random access process with the base station, and includes following steps. The wireless communication device transmits a preamble code to the base station, obtains an indicator in a packet transmitted from the base station, and determines whether to obtain a first random access response and a second random access response according to the indicator. When the transmission of the preamble code by the wireless communication device encounters a collision and the indicator is set the wireless communication device performs a random access process by using the command in the first random access response. Otherwise, the wireless communication device performs the conventional process.

摘要翻译： 提供了一种随机存取方法，参数分配方法，无线通信装置和使用该方法的基站。 随机接入方法适用于无线通信设备与基站进行随机接入过程，并且包括以下步骤。 无线通信装置向基站发送前导码，获取从基站发送的分组中的指示符，并根据该指标确定是否获得第一随机接入响应和第二随机接入响应。 当由无线通信设备发送前导码遇到冲突时，无线通信设备通过使用第一随机接入响应中的命令来执行随机接入过程。 否则，无线通信装置执行常规处理。