公开(公告)号：US08258827B2

公开(公告)日：2012-09-04

申请号：US12789424

申请日：2010-05-27

申请人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B19/00

CPC分类号： H03B19/14

摘要： A frequency doubler receiving an in-phase oscillating signal and an inverse oscillating signal and generating an output signal oscillating at a multiplied frequency, accordingly. The frequency doubler has a first transistor, a second transistor, a first inductor and a second inductor. A first terminal of the first transistor and a first terminal of the second transistor are at a common voltage. The frequency doubler receives the in-phase oscillating signal and the inverse oscillating signal via control terminals of the first and second transistors. The first and second inductors couple a second terminal of the first transistor and a second terminal of the second transistor to an output terminal of the frequency doubler, respectively. The first and second inductors may be separate inductance devices or, in another case, be implemented by a symmetric inductor.

摘要翻译： 接收同相振荡信号的倍频器和反相振荡信号，并相应地产生以倍频振荡的输出信号。 倍频器具有第一晶体管，第二晶体管，第一电感器和第二电感器。 第一晶体管的第一端子和第二晶体管的第一端子处于公共电压。 倍频器通过第一和第二晶体管的控制端接收同相振荡信号和反相振荡信号。 第一和第二电感分别将第一晶体管的第二端子和第二晶体管的第二端子耦合到倍频器的输出端子。 第一和第二电感器可以是分离的电感器件，或者在另一种情况下可由对称电感器来实现。

公开(公告)号：US08035457B2

公开(公告)日：2011-10-11

申请号：US12687891

申请日：2010-01-15

申请人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B5/08

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1225 ,  H03B5/1253 ,  H03B5/1271 ,  H03B5/1296

摘要： A voltage controlled oscillator (VCO) includes a voltage controlled current source (VCCS), a negative resistance circuit (NRC), a first transformer, a second transformer, a first transistor and a second transistor. A current terminal of the VCCS receives a control voltage. First terminals of first and second current paths in the NRC are coupled to a current terminal of the VCCS. Primary sides of the first and the second transformers are respectively coupled to second terminals of the first and the second current paths. Secondary sides of the first and the second transformers are first and second output terminals of the VCO, respectively. First terminals of the first and the second transistor are respectively coupled to the secondary sides of the first and the second transformers. Control terminals of the first and the second transformers are respectively coupled to the primary sides of the first and the second transformers.

摘要翻译： 压控振荡器（VCO）包括压控电流源（VCCS），负电阻电路（NRC），第一变压器，第二变压器，第一晶体管和第二晶体管。 VCCS的电流端子接收控制电压。 NRC中的第一和第二电流路径的第一端子耦合到VCCS的电流端子。 第一和第二变压器的主侧分别耦合到第一和第二电流路径的第二端。 第一和第二变压器的次级侧分别是VCO的第一和第二输出端。 第一和第二晶体管的第一端分别耦合到第一和第二变压器的次级侧。 第一变压器和第二变压器的控制端子分别与第一变压器和第二变压器的一次侧接合。

公开(公告)号：US20110175651A1

公开(公告)日：2011-07-21

申请号：US12789424

申请日：2010-05-27

申请人： Chih-Hsiang CHANG ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang CHANG ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B19/06 ,  H03B19/00

CPC分类号： H03B19/14

摘要： A frequency doubler receiving an in-phase oscillating signal and an inverse oscillating signal and generating an output signal oscillating at a multiplied frequency, accordingly. The frequency doubler has a first transistor, a second transistor, a first inductor and a second inductor. A first terminal of the first transistor and a first terminal of the second transistor are at a common voltage. The frequency doubler receives the in-phase oscillating signal and the inverse oscillating signal via control terminals of the first and second transistors. The first and second inductors couple a second terminal of the first transistor and a second terminal of the second transistor to an output terminal of the frequency doubler, respectively. The first and second inductors may be separate inductance devices or, in another case, be implemented by a symmetric inductor.

摘要翻译： 接收同相振荡信号的倍频器和反相振荡信号，并相应地产生以倍频振荡的输出信号。 倍频器具有第一晶体管，第二晶体管，第一电感器和第二电感器。 第一晶体管的第一端子和第二晶体管的第一端子处于公共电压。 倍频器通过第一和第二晶体管的控制端接收同相振荡信号和反相振荡信号。 第一和第二电感分别将第一晶体管的第二端子和第二晶体管的第二端子耦合到倍频器的输出端子。 第一和第二电感器可以是分离的电感器件，或者在另一种情况下可由对称电感器来实现。

公开(公告)号：US20110018645A1

公开(公告)日：2011-01-27

申请号：US12687891

申请日：2010-01-15

申请人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B7/00 ,  H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1225 ,  H03B5/1253 ,  H03B5/1271 ,  H03B5/1296

摘要： A voltage controlled oscillator (VCO) includes a voltage controlled current source (VCCS), a negative resistance circuit (NRC), a first transformer, a second transformer, a first transistor and a second transistor. A current terminal of the VCCS receives a control voltage. First terminals of first and second current paths in the NRC are coupled to a current terminal of the VCCS. Primary sides of the first and the second transformers are respectively coupled to second terminals of the first and the second current paths. Secondary sides of the first and the second transformers are first and second output terminals of the VCO, respectively. First terminals of the first and the second transistor are respectively coupled to the secondary sides of the first and the second transformers. Control terminals of the first and the second transformers are respectively coupled to the primary sides of the first and the second transformers.

摘要翻译： 压控振荡器（VCO）包括压控电流源（VCCS），负电阻电路（NRC），第一变压器，第二变压器，第一晶体管和第二晶体管。 VCCS的电流端子接收控制电压。 NRC中的第一和第二电流路径的第一端子耦合到VCCS的电流端子。 第一和第二变压器的主侧分别耦合到第一和第二电流路径的第二端。 第一和第二变压器的次级侧分别是VCO的第一和第二输出端。 第一和第二晶体管的第一端分别耦合到第一和第二变压器的次级侧。 第一变压器和第二变压器的控制端子分别与第一变压器和第二变压器的一次侧接合。

公开(公告)号：US20120154060A1

公开(公告)日：2012-06-21

申请号：US13018378

申请日：2011-01-31

申请人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1243 ,  H03B27/00

摘要： A quadrature voltage-controlled oscillator (QVCO) apparatus including a first VCO, a second VCO, a first energy-storage element, a second energy-storage element, a third energy-storage element and a fourth energy-storage element is provided. The first VCO has a first and a second phase output ends. The second VCO has a third and a fourth phase output ends. A first and a second ends of the first energy-storage element respectively connect to the first and the third phase output ends. A first and a second ends of the second energy-storage element respectively connect to the second and the third phase output ends. A first and a second ends of the third energy-storage element respectively connect to the second and the fourth phase output ends. A first and a second ends of the fourth energy-storage element respectively connect to the first and the fourth phase output ends.

摘要翻译： 提供了包括第一VCO，第二VCO，第一能量存储元件，第二能量存储元件，第三能量存储元件和第四能量存储元件的正交压控振荡器（QVCO）装置。 第一个VCO具有第一和第二相输出端。 第二个VCO具有第三和第四相输出端。 第一能量存储元件的第一端和第二端分别连接到第一和第三相输出端。 第二能量存储元件的第一端和第二端分别连接到第二和第三相输出端。 第三储能元件的第一和第二端分别连接到第二和第四相输出端。 第四能量存储元件的第一和第二端分别连接到第一和第四相输出端。

公开(公告)号：US08723609B2

公开(公告)日：2014-05-13

申请号：US13558360

申请日：2012-07-26

申请人： Chih-Hsiang Chang ,  Nai-Chen Cheng ,  Yu Lee ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Nai-Chen Cheng ,  Yu Lee ,  Ching-Yuan Yang

IPC分类号： H03B5/12 ,  H03B19/14 ,  H03B27/00 ,  H03C3/22 ,  H03L7/24

CPC分类号： H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1243 ,  H03B5/1296 ,  H03B19/14 ,  H03B27/00 ,  H03B2200/004 ,  H03B2200/0078 ,  H03B2201/0208 ,  H03L7/24

摘要： A voltage-controlled oscillator (VCO) module including a first VCO unit, a second VCO unit, and a matching circuit is provided. The first VCO unit includes a first terminal and a second terminal and generates a first oscillator signal. The second VCO unit is coupled to the first VCO unit and generates a second oscillator signal. The matching circuit is coupled between the first VCO unit and second VCO unit. The matching circuit includes a plurality of inductor modules respectively coupled between the first terminal of the first VCO unit and the second VCO unit, between the first terminal and the second terminal of the first VCO unit, and between the second terminal of the first VCO unit and the second VCO unit. Furthermore, a method for generating oscillator signals is also provided.

摘要翻译： 提供了包括第一VCO单元，第二VCO单元和匹配电路的压控振荡器（VCO）模块。 第一VCO单元包括第一端子和第二端子，并产生第一振荡器信号。 第二VCO单元耦合到第一VCO单元并产生第二振荡器信号。 匹配电路耦合在第一VCO单元和第二VCO单元之间。 匹配电路包括分别耦合在第一VCO单元的第一端和第二VCO单元之间的多个电感器模块，位于第一VCO单元的第一端子和第二端子之间，并且在第一VCO单元的第二端子之间 和第二个VCO单元。 此外，还提供了一种用于产生振荡器信号的方法。

公开(公告)号：US20130241661A1

公开(公告)日：2013-09-19

申请号：US13558360

申请日：2012-07-26

申请人： Chih-Hsiang Chang ,  Nai-Chen Cheng ,  Yu Lee ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Nai-Chen Cheng ,  Yu Lee ,  Ching-Yuan Yang

IPC分类号： H03B5/12

CPC分类号： H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1243 ,  H03B5/1296 ,  H03B19/14 ,  H03B27/00 ,  H03B2200/004 ,  H03B2200/0078 ,  H03B2201/0208 ,  H03L7/24

摘要： A voltage-controlled oscillator (VCO) module including a first VCO unit, a second VCO unit, and a matching circuit is provided. The first VCO unit includes a first terminal and a second terminal and generates a first oscillator signal. The second VCO unit is coupled to the first VCO unit and generates a second oscillator signal. The matching circuit is coupled between the first VCO unit and second VCO unit. The matching circuit includes a plurality of inductor modules respectively coupled between the first terminal of the first VCO unit and the second VCO unit, between the first terminal and the second terminal of the first VCO unit, and between the second terminal of the first VCO unit and the second VCO unit. Furthermore, a method for generating oscillator signals is also provided.

摘要翻译： 提供了包括第一VCO单元，第二VCO单元和匹配电路的压控振荡器（VCO）模块。 第一VCO单元包括第一端子和第二端子，并产生第一振荡器信号。 第二VCO单元耦合到第一VCO单元并产生第二振荡器信号。 匹配电路耦合在第一VCO单元和第二VCO单元之间。 匹配电路包括分别耦合在第一VCO单元的第一端和第二VCO单元之间的多个电感器模块，位于第一VCO单元的第一端子和第二端子之间，并且在第一VCO单元的第二端子之间 和第二个VCO单元。 此外，还提供了一种用于产生振荡器信号的方法。

公开(公告)号：US20100040182A1

公开(公告)日：2010-02-18

申请号：US12266530

申请日：2008-11-06

申请人： Ching-Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

发明人： Ching-Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0041 ,  H04L7/0087 ,  H04Q11/0067 ,  H04Q2011/0079

摘要： A bust-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase.

摘要翻译： 提供了采用相位选择技术的突发模式时钟和数据恢复电路。 在数据恢复电路中，使用锁相环（PLL）电路来提供多个具有时钟相位的固定时钟信号。 过采样相位选择电路耦合到锁相环电路，用于通过使用时钟信号检测接收数据信号的数据沿，并根据数据沿的位置选择要锁定的时钟相位。 延迟锁定回路（DLL）电路耦合到锁相环电路和过采样相位选择电路，并用于将数据信号的数据相位与所选择的时钟信号的时钟相位进行比较，以便延迟 数据信号的数据相位延迟一个延迟时间，直到数据相位被锁定为时钟相位。

公开(公告)号：US20120146693A1

公开(公告)日：2012-06-14

申请号：US13114030

申请日：2011-05-23

申请人： Yu Lee ,  Nai-Chen Cheng ,  Ji-Jan Chen ,  Yuan-Hua Chu ,  Ching-Yuan Yang

发明人： Yu Lee ,  Nai-Chen Cheng ,  Ji-Jan Chen ,  Yuan-Hua Chu ,  Ching-Yuan Yang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G06F1/10 ,  G06F1/12 ,  H03L7/07 ,  H03L7/0812 ,  H04L7/0008

摘要： An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.

摘要翻译： 提供了一种用于时钟偏移补偿的装置。 该装置包括设置在第一管芯中的第一延迟锁定环（DLL）模块和设置在第二管芯中的第二DLL模块。 第一DLL模块的第一输入端接收参考时钟。 第二DLL模块的第一输入端电连接到第一DLL模块的输出端。 第二DLL模块的输出端电连接到第一DLL模块的第二输入端。

公开(公告)号：US06754841B2

公开(公告)日：2004-06-22

申请号：US09842723

申请日：2001-04-27

申请人： Ching-Yuan Yang

发明人： Ching-Yuan Yang

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A one-wire clock-skew compensating method and a circuit for the method are disclosed to solve the clock-skew problem in transmission of clock signals in a high-speed synchronous circuit such as of a CPU, hence the clock of a remote circuit and the clock input of the system can be accurately synchronized. The method is based on the principle of identical propagation delay on the forward and reverse paths at the two ends of one wire in transmission and receiving; a clock-deskew buffer composing a delay locked loop and a bidirectional buffer is provided in the front of the signal transmission end of the wire, while the other end of the wire has a bidirectional buffer too, hence signals are transmitted bidirectionally at the same time on the wire. When a signal is transmitted from the clock-deskew buffer to the latter bidirectional buffer through the forward and reverse paths, its arrival time is accurately controlled to avoid errors in dealing with signals due to phase difference between a reference clock and a remote clock as in conventional techniques.

摘要翻译： 公开了一种用于该方法的单线时钟偏移补偿方法和电路，以解决诸如CPU之类的高速同步电路中的时钟信号传输中的时钟偏移问题，因此远程电路的时钟和 系统的时钟输入可以精确同步。 该方法基于传输和接收中一根线两端的正向和反向路径上传播延迟相同的原理; 构成延迟锁定环和双向缓冲器的时钟 - 消隐缓冲器被提供在线的信号发送端的前方，而线的另一端也具有双向缓冲器，因此信号同时被双向传输 在线上 当通过正向和反向路径将信号从时钟 - 消隐缓冲器发送到后一个双向缓冲器时，其到达时间被精确地控制，以避免由于参考时钟和远程时钟之间的相位差而在处理信号时出现错误，如 常规技术。