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    SUPPORTING STRUCTURE MODULE AND ELECTRONIC DEVICE USING THE SAME
    2.
    发明申请
    SUPPORTING STRUCTURE MODULE AND ELECTRONIC DEVICE USING THE SAME 有权
    支持结构模块和使用该模块的电子设备

    公开(公告)号：US20110310541A1

    公开(公告)日：2011-12-22

    申请号：US13160519

    申请日：2011-06-15

    Applicant: Jiun-Lin Wu ,  Chia-Hsiang Hsiang ,  Ching-Hao Yu

    Inventor： Jiun-Lin Wu ,  Chia-Hsiang Hsiang ,  Ching-Hao Yu

    IPC: H05K5/00 ,  E05F1/12 ,  F16M13/02 ,  E05D11/00

    CPC classification number: G06F1/1681 ,  E05Y2900/606 ,  F16M13/005 ,  F16M2200/022 ,  Y10T16/533 ,  Y10T16/54038

    Abstract: This disclosure provides a supporting structure module and an electronic device using the same. The supporting structure module in the invention is used in the electronic device. The electronic device includes a first casing, a hinge, and a second casing rotatable relative to the first casing via the hinge. The supporting structure module includes a first supporting structure, and the first supporting structure includes a first bracket and a first hinge cover. The first bracket is fixed to and exposed from the first casing. The first hinge cover is connected with the first bracket by integral forming, and the first hinge cover is exposed from the first casing and covers a part of the hinge.

    Abstract translation: 本公开提供了一种支撑结构模块和使用其的电子装置。 本发明的支撑结构模块用于电子设备。 该电子设备包括第一壳体，铰链以及经由铰链相对于第一壳体可旋转的第二壳体。 支撑结构模块包括第一支撑结构，第一支撑结构包括第一支架和第一铰链盖。 第一支架固定到第一壳体并暴露于第一壳体。 第一铰链盖通过一体成型与第一支架连接，第一铰链盖从第一壳体露出并覆盖铰链的一部分。

    MULTI-CHANNEL MEMORY APPARATUS AND METHOD THEREOF
    3.
    发明申请
    MULTI-CHANNEL MEMORY APPARATUS AND METHOD THEREOF 有权
    多通道存储器及其方法

    公开(公告)号：US20110126079A1

    公开(公告)日：2011-05-26

    申请号：US12624553

    申请日：2009-11-24

    Applicant: Chien-Chung Wu ,  Ching-Hao Yu ,  Li-Lien Lin ,  Chao-Yi Wu

    Inventor： Chien-Chung Wu ,  Ching-Hao Yu ,  Li-Lien Lin ,  Chao-Yi Wu

    IPC: G11C29/00 ,  G06F11/00

    CPC classification number: G06F11/1044

    Abstract: A multi-channel memory apparatus is provided. The multi-channel memory apparatus includes a host interface, storage channels, an error correcting module, and a multiple memory access module. The host interface is arranged to receive and transmit data from and to a host device. Each storage channel is coupled to a memory device for storing the data. The error correcting module is shared by the storage channels, includes an error correction code engine and a data buffer, and is arranged to perform error correction code encoding on the data to be stored into the memory devices and perform error correction code decoding on the data read out from the memory devices. The multiple memory access module is coupled between the storage channels and the error correcting module and arranged to perform multiple access control of the storage channels for the error correcting module.

    Abstract translation: 提供了一种多通道存储装置。 多通道存储装置包括主机接口，存储通道，纠错模块和多存储器访问模块。 主机接口被布置成从主机设备接收和发送数据。 每个存储通道耦合到用于存储数据的存储器件。 纠错模块由存储通道共享，包括纠错码引擎和数据缓冲器，并且被配置为对要存储到存储器件中的数据执行纠错码编码，并对数据执行纠错码解码 从内存设备中读出。 多存储器访问模块耦合在存储通道和纠错模块之间，并被布置为对错误校正模块执行存储通道的多次访问控制。

    Supporting structure module and electronic device using the same
    6.
    发明授权
    Supporting structure module and electronic device using the same 有权
    支持结构模块和电子设备使用相同

    公开(公告)号：US08526171B2

    公开(公告)日：2013-09-03

    申请号：US13160519

    申请日：2011-06-15

    Applicant: Jiun-Lin Wu ,  Chia-Hsiang Hsiang ,  Ching-Hao Yu

    Inventor： Jiun-Lin Wu ,  Chia-Hsiang Hsiang ,  Ching-Hao Yu

    IPC: G06F1/16

    CPC classification number: G06F1/1681 ,  E05Y2900/606 ,  F16M13/005 ,  F16M2200/022 ,  Y10T16/533 ,  Y10T16/54038

    Abstract: This disclosure provides a supporting structure module and an electronic device using the same. The supporting structure module in the invention is used in the electronic device. The electronic device includes a first casing, a hinge, and a second casing rotatable relative to the first casing via the hinge. The supporting structure module includes a first supporting structure, and the first supporting structure includes a first bracket and a first hinge cover. The first bracket is fixed to and exposed from the first casing. The first hinge cover is connected with the first bracket by integral forming, and the first hinge cover is exposed from the first casing and covers a part of the hinge.

    Abstract translation: 本公开提供了一种支撑结构模块和使用其的电子装置。 本发明的支撑结构模块用于电子设备。 该电子设备包括第一壳体，铰链以及经由铰链相对于第一壳体可旋转的第二壳体。 支撑结构模块包括第一支撑结构，第一支撑结构包括第一支架和第一铰链盖。 第一支架固定到第一壳体并暴露于第一壳体。 第一铰链盖通过一体成型与第一支架连接，第一铰链盖从第一壳体露出并覆盖铰链的一部分。

    STORAGE CONTROLLER HAVING SOFT DECODER INCLUDED THEREIN, RELATED STORAGE CONTROL METHOD THEREOF AND SYSTEM USING THE SAME
    7.
    发明申请
    STORAGE CONTROLLER HAVING SOFT DECODER INCLUDED THEREIN, RELATED STORAGE CONTROL METHOD THEREOF AND SYSTEM USING THE SAME 审中-公开
    具有软件解码器的存储控制器及其相关的存储控制方法及其使用的系统

    公开(公告)号：US20100251076A1

    公开(公告)日：2010-09-30

    申请号：US12646936

    申请日：2009-12-23

    Applicant: Chao-Yi Wu ,  Li-Lien Lin ,  Chien-Chung Wu ,  Ching-Hao Yu

    Inventor： Chao-Yi Wu ,  Li-Lien Lin ,  Chien-Chung Wu ,  Ching-Hao Yu

    IPC: H03M13/45 ,  G06F11/10

    CPC classification number: H03M13/152 ,  G06F11/1068 ,  H03M13/6516

    Abstract: An exemplary storage controller for controlling data access of a storage device includes a control circuit and a soft decoder. The control circuit is utilized for reading data from the storage device to obtain readout data. The soft decoder is coupled to the control circuit, and utilized for performing a soft decoding operation upon the readout data to generate decoded data. The soft decoder may be a low density parity check (LDPC) decoder, a block turbo code (BTC) decoder, or a convolutional turbo code (CTC) decoder. The storage device may be a flash memory device.

    Abstract translation: 用于控制存储设备的数据访问的示例性存储控制器包括控制电路和软解码器。 控制电路用于从存储装置读取数据以获得读出数据。 软解码器耦合到控制电路，用于对读出的数据执行软解码操作以产生解码的数据。 软解码器可以是低密度奇偶校验（LDPC）解码器，块turbo码（BTC）解码器或卷积turbo码（CTC）解码器。 存储设备可以是闪存设备。

    Multi-channel memory apparatus and method thereof
    9.
    发明授权
    Multi-channel memory apparatus and method thereof 有权
    多通道存储装置及其方法

    公开(公告)号：US08510631B2

    公开(公告)日：2013-08-13

    申请号：US12624553

    申请日：2009-11-24

    Applicant: Chien-Chung Wu ,  Ching-Hao Yu ,  Li-Lien Lin ,  Chao-Yi Wu

    Inventor： Chien-Chung Wu ,  Ching-Hao Yu ,  Li-Lien Lin ,  Chao-Yi Wu

    IPC: G06F11/00

    CPC classification number: G06F11/1044

    Abstract: A multi-channel memory apparatus is provided. The multi-channel memory apparatus includes a host interface, storage channels, an error correcting module, and a multiple memory access module. The host interface is arranged to receive and transmit data from and to a host device. Each storage channel is coupled to a memory device for storing the data. The error correcting module is shared by the storage channels, includes an error correction code engine and a data buffer, and is arranged to perform error correction code encoding on the data to be stored into the memory devices and perform error correction code decoding on the data read out from the memory devices. The multiple memory access module is coupled between the storage channels and the error correcting module and arranged to perform multiple access control of the storage channels for the error correcting module.

    Abstract translation: 提供了一种多通道存储装置。 多通道存储装置包括主机接口，存储通道，纠错模块和多存储器访问模块。 主机接口被布置成从主机设备接收和发送数据。 每个存储通道耦合到用于存储数据的存储器件。 纠错模块由存储通道共享，包括纠错码引擎和数据缓冲器，并且被配置为对要存储到存储器件中的数据执行纠错码编码，并对数据执行纠错码解码 从内存设备中读出。 多存储器访问模块耦合在存储通道和纠错模块之间，并被布置为对错误校正模块执行存储通道的多次访问控制。

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