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公开(公告)号：US20090189591A1
公开(公告)日：2009-07-30
申请号：US12021484
申请日：2008-01-29
CPC分类号： G05F3/30
摘要： In temperature sensing circuitry PTAT (Proportional to Absolute Temperature) Voltage References are typically used. By adding a feedback circuit and a source follower into the classic design, the circuit can guarantee that the current is mirrored identically regardless of the value of power supply voltage. This added circuitry is easy to implement and is low in both power and area. The essence of this invention is that the PTAT circuit allows a large range of operation including low voltage (1 Volt) and more accurate temperature readings.
摘要翻译： 在温度感测电路PTAT（与绝对温度成比例）中，通常使用电压基准。 通过在经典设计中添加反馈电路和源极跟随器，电路可以保证电流相同，无论电源电压的值如何。 这种增加的电路容易实现，功率和面积都很小。 本发明的实质是PTAT电路允许包括低电压（1伏）和更准确的温度读数的大范围的操作。
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公开(公告)号：US07271643B2
公开(公告)日：2007-09-18
申请号：US11138102
申请日：2005-05-26
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrically blowable fuse circuit having a fuse which may be placed in a condition to be blown. The circuit includes a first transistor having a body, a source, a drain, and a gate. The source is connected to one end of the fuse and the drain is connected to ground. The first transistor further includes a controllable parasitic device in its body. A second transistor is connected to the parasitic device such that when the second transistor is turned on, the parasitic device turns on the first transistor, allowing the fuse to be blown when the fuse is placed in a condition to be blown.
摘要翻译： 一种具有熔断器的可电熔熔断器电路，该保险丝可被放置在要被吹制的状态。 电路包括具有主体，源极，漏极和栅极的第一晶体管。 源极连接到保险丝的一端，漏极连接到地。 第一晶体管还包括其体内的可控寄生器件。 第二晶体管连接到寄生器件，使得当第二晶体管导通时，寄生器件接通第一晶体管，当保险丝置于待熔断状态时，允许保险丝熔断。
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公开(公告)号：US6023577A
公开(公告)日：2000-02-08
申请号：US938676
申请日：1997-09-26
CPC分类号： G06F17/5036
摘要： A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that, current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts. To solve the problem of predicting the delay in a delay predictor (for example, NDR rules generation), the offset from the body voltage as a part of the best case/worst case determination is included.
摘要翻译： 用于编码为用于基于SOI的FET逻辑设计的设计软件的电子设计模型中的方法包括在模拟期间的任何时间，模拟SOI器件并将浮动体电压设置为任何所需值，通过向模型添加理想 电压源，其值是期望的体电压，与理想电流源串联，其值为恒定倍数的电压。 当常数为零时，电流不能流动，任何附加的组件对电路都没有影响。 当常数不为零时，所述理想电流源似乎与电阻器相同，使得电流可以流入或流出体节点，从而设定其电压。 恒定值始终保持为零，除非需要改变体电压。 可以随时重置体电压，以解决一次模拟运行中连续延迟的问题，并在每次延迟测量开始之前复位电压。 为了解决预测延迟预测器中的延迟（例如，NDR规则生成）的问题，包括作为最佳情况/最坏情况判定的一部分的与体电压的偏移。
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公开(公告)号：US08237513B2
公开(公告)日：2012-08-07
申请号：US12821526
申请日：2010-06-23
CPC分类号： H03L3/00
摘要： A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.
摘要翻译： 用于锁相环（PLL）的压控振荡器（VCO）包括启动振荡器，所述启动振荡器包括第一多个反相器; 主振荡器，所述主振荡器包括第二多个反相器，其中所述第二多个反相器的数量少于所述第一多个反相器的数量; 以及连接到启动振荡器和主振荡器的控制模块。 一种在锁相环（PLL）中操作压控振荡器（VCO）的方法，包括启动振荡器和主振荡器的VCO包括向启动振荡器发送使能信号; 等待预定数量的启动振荡器时钟周期; 并且当经过预定数量的启动振荡器时钟周期时，向启动振荡器发送禁止信号，并向主振荡器发送使能信号。
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公开(公告)号：US20110316593A1
公开(公告)日：2011-12-29
申请号：US12821526
申请日：2010-06-23
IPC分类号： H03L7/06
CPC分类号： H03L3/00
摘要： A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.
摘要翻译： 用于锁相环（PLL）的压控振荡器（VCO）包括启动振荡器，所述启动振荡器包括第一多个反相器; 主振荡器，所述主振荡器包括第二多个反相器，其中所述第二多个反相器的数量少于所述第一多个反相器的数量; 以及连接到启动振荡器和主振荡器的控制模块。 一种在锁相环（PLL）中操作压控振荡器（VCO）的方法，包括启动振荡器和主振荡器的VCO包括向启动振荡器发送使能信号; 等待预定数量的启动振荡器时钟周期; 并且当经过预定数量的启动振荡器时钟周期时，向启动振荡器发送禁止信号，并向主振荡器发送使能信号。
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6.发明授权PLL loop filter capacitor test circuit and method for on chip testing of analog leakage of a circuit 失效PLL环路滤波电容测试电路及芯片模拟电路漏电测试方法公开(公告)号：US07078887B1
公开(公告)日：2006-07-18
申请号：US11040138
申请日：2005-01-21
IPC分类号： G01R23/12
CPC分类号： G01R27/02 , G01R31/2639 , G01R31/2884
摘要： A test circuit within an existing design to enable the test circuit to test directly within the circuit. This invention provides a way to test and measure the leakage of the PLL loop filter capacitor leakage during test with a simple digital tester using existing pins. The test PLL circuit has circuit a plurality of capacitors and responsive amplifiers circuits for measuring leakage including a first capacitor set having multiple transistors coupled in series and with a reference resistor circuit coupled to a first amplifier and a second capacitor set having multiple transistors coupled in series and said reference resistor circuit coupled to a second amplifier to measure the leaking across the respective capacitors coupled to said first and second amplifiers and to provide an output of the leakage for measurement with the output of said first and second amplifiers. The reference resistor circuit is broken into several series resistors and additional transistors and resistors are supplied with their terminals shorted out, to allow for RIT-B circuit tuning. The output of the test circuit provides the measurement of analog leakage to a digital tester for testing of chips having the circuit during manufacturing test.
摘要翻译： 现有设计中的测试电路，使测试电路能够在电路内直接测试。 本发明提供了一种在使用现有引脚的简单数字测试仪中测试和测量测试期间PLL环路滤波电容器漏电泄漏的方法。 测试PLL电路具有用于测量泄漏的多个电容器和响应放大器电路，包括具有串联耦合的多个晶体管的第一电容器组和耦合到第一放大器的参考电阻器电路和具有串联耦合的多个晶体管的第二电容器组 并且所述参考电阻器电路耦合到第二放大器以测量穿过耦合到所述第一和第二放大器的相应电容器的泄漏，并且提供所述泄漏的输出与所述第一和第二放大器的输出进行测量。 参考电阻电路分为几个串联电阻，额定的晶体管和电阻的端子短路，以允许RIT-B电路调谐。 测试电路的输出提供了对数字测试仪的模拟泄漏测量，用于在制造测试期间测试具有电路的芯片。
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7.发明授权Circuits associated with fusible elements for establishing and detecting of the states of those elements 失效与可熔元件相关联的电路，用于建立和检测这些元件的状态公开(公告)号：US06972614B2
公开(公告)日：2005-12-06
申请号：US10820092
申请日：2004-04-07
申请人： Mark E. Anderson, II , Sundar K. Iyer , Chandrasekara Kothandaraman , Edward P. Maciejewski , George E. Smith, III
发明人： Mark E. Anderson, II , Sundar K. Iyer , Chandrasekara Kothandaraman , Edward P. Maciejewski , George E. Smith, III
摘要： An identification circuit for establishing and sensing the state of a fusible element used in on chip identification of the chip's type comprising: a circuit establishing control signals for turning the identification circuit on and off; dual paths energized by the control signals generated by the level setting circuit to energize one path through the fusible element to provide a state level and the other path through a reference path which provides a reference voltage level which is distinguishable from both the blown and unblown states of the fusible element; a differential sensing circuit for comparing the reference voltage level to the state level to provide a signal indicating the state of the fusible element; and protection circuitry to protect the circuit during an operation in which the state of the fusible element is set.
摘要翻译： 一种识别电路，用于建立和感测用于芯片类型片上识别的可熔元件的状态，包括：建立用于打开和关闭识别电路的控制信号的电路; 通过由电平设置电路产生的控制信号激励的双路径，以激励通过可熔元件的一条路径，以提供状态电平，并且通过参考路径的另一条路径，该参考路径提供可与吹制状态和非吹出状态区分的参考电压电平 的易熔元素; 差分感测电路，用于将参考电压电平与状态电平进行比较，以提供指示可熔元件的状态的信号; 以及用于在设置可熔元件的状态的操作期间保护电路的保护电路。
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公开(公告)号：US06177708B1
公开(公告)日：2001-01-23
申请号：US09324324
申请日：1999-06-02
IPC分类号： H01L2941
CPC分类号： H01L27/1203 , H01L29/42384 , H01L29/78606 , H01L29/78618
摘要： A self-aligned SOI FET device with an “L” shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a “T” shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.
摘要翻译： 具有“L”形栅极结构的自对准SOI FET器件允许在器件的源极和主体之间形成整体二极管结。 具有该栅极几何形状的两个器件可以有利地并排布置在可容纳但具有“T”形栅极结构的单个器件的单个rx开口中。 根据本发明的教导的器件可以使用标准的现有技术的SOI处理步骤容易地形成。 本发明的一个方面包括使用这些新颖的SOI器件，其主体和源极在诸如存储器单元读出放大器的电路应用中连接在一起，其中高速操作表示使用SOI技术，但是物理空间考虑限制了它们的应用 。
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公开(公告)号：US6154091A
公开(公告)日：2000-11-28
申请号：US324498
申请日：1999-06-02
IPC分类号： H01L27/12 , H01L29/423 , H01L29/786 , H01L25/00
CPC分类号： H01L29/78615 , H01L27/1203 , H01L29/4238 , H01L29/42384
摘要： A self-aligned SOI FET device with an "L" shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a "T" shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.
摘要翻译： 具有“L”形栅极结构的自对准SOI FET器件允许在器件的源极和主体之间形成整体二极管结。 具有该栅极几何形状的两个器件可以有利地并排布置在可容纳但具有“T”形栅极结构的单个器件的单个rx开口中。 根据本发明的教导的器件可以使用标准的现有技术的SOI处理步骤容易地形成。 本发明的一个方面包括使用这些新颖的SOI器件，其主体和源极在诸如存储器单元读出放大器的电路应用中连接在一起，其中高速操作表示使用SOI技术，但是物理空间考虑限制了它们的应用 。
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公开(公告)号：US6141632A
公开(公告)日：2000-10-31
申请号：US388594
申请日：1999-09-02
申请人： George E. Smith, III , Fariborz Assaderaghi , Paul D. Muench , Lawrence F. Wagner, Jr. , Timothy L. Walters
发明人： George E. Smith, III , Fariborz Assaderaghi , Paul D. Muench , Lawrence F. Wagner, Jr. , Timothy L. Walters
CPC分类号： G06F17/5036
摘要： A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device by and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero, no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts. To solve the problem of predicting the delay in a delay predictor (for example, delay rules generation), the offset from the body voltage as a part of the best case/worst case determination is included. The improved process employs a topological analysis for circuit elements to determine whether the element falls in one of several categories, and in the process determines which elements of a circuit might be in AC equilibrium.
摘要翻译： 用于编码为用于基于SOI的FET逻辑设计的设计软件的电子设计模型中的方法包括通过在仿真期间的任何时间对浮动体电压进行模拟并将浮体电压设置为任何期望值，通过向模型添加 理想的电压源，其值是期望的体电压，与理想电流源串联，其值是恒定倍数自身的电压。 当常数为零时，不会流过电流，任何附加组件对电路都没有影响。 当常数不为零时，所述理想电流源似乎与电阻器相同，使得电流可以流入或流出身体节点，从而设定其电压。 恒定值始终保持为零，除非需要改变体电压。 可以随时重置体电压，以解决一次模拟运行中连续延迟的问题，并在每次延迟测量开始之前复位电压。 为了解决预测延迟预测器中的延迟（例如，延迟规则生成）的问题，包括作为最佳情况/最坏情况确定的一部分的与体电压的偏移。 改进的过程采用电路元件的拓扑分析来确定元件是否属于几个类别之一，并且在该过程中确定电路的哪些元件可能处于AC平衡状态。
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