公开(公告)号：US08526219B2

公开(公告)日：2013-09-03

申请号：US13367495

申请日：2012-02-07

申请人： Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

发明人： Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.

摘要翻译： 存储电路包括多个位线结构（每个都包括真和互补位线），多个字线结构与多个位线结构相交以形成多个单元位置; 以及位于多个单元位置的多个单元。 每个单元包括逻辑存储元件，选择性地将给定的一个真位线耦合到逻辑存储元件的第一存取晶体管和选择性地将对应的给定的一个互补位线耦合到逻辑存储器的第二存取晶体管 元件。 第一和第二存取晶体管中的一个或两个被配置为具有不对称电流特性，以实现READ和WRITE边缘的独立增强。 还包括在6-T范围内的是包括在机器可读介质中的一个或多个设计结构，包括如本文所述的电路。

公开(公告)号：US20120185817A1

公开(公告)日：2012-07-19

申请号：US13367495

申请日：2012-02-07

申请人： Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

发明人： Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

IPC分类号： G06F17/50

CPC分类号： G11C11/412

摘要： A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.

摘要翻译： 存储电路包括多个位线结构（每个都包括真和互补位线），多个字线结构与多个位线结构相交以形成多个单元位置; 以及位于多个单元位置的多个单元。 每个单元包括逻辑存储元件，选择性地将给定的一个真位线耦合到逻辑存储元件的第一存取晶体管和选择性地将对应的给定的一个互补位线耦合到逻辑存储器的第二存取晶体管 元件。 第一和第二存取晶体管中的一个或两个被配置为具有不对称电流特性，以实现READ和WRITE边缘的独立增强。 还包括在6-T范围内的是包括在机器可读介质中的一个或多个设计结构，包括如本文所述的电路。

公开(公告)号：US08139400B2

公开(公告)日：2012-03-20

申请号：US12017404

申请日：2008-01-22

申请人： Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

发明人： Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

IPC分类号： G11C11/00 ,  H01L29/02

CPC分类号： G11C11/412

摘要： A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.

摘要翻译： 存储器电路包括多个位线结构（每个都包括真和互补位线），与多个位线结构相交以形成多个单元位置的多个字线结构和位于该位线的多个单元 多个单元位置。 每个单元包括逻辑存储元件，选择性地将给定的一个真位线耦合到逻辑存储元件的第一存取晶体管和选择性地将对应的给定的一个互补位线耦合到逻辑存储器的第二存取晶体管 元件。 第一和第二存取晶体管中的一个或两个被配置为具有不对称电流特性，以实现READ和WRITE边缘的独立增强。 还包括在6-T范围内的是包括在机器可读介质中的一个或多个设计结构，包括如本文所述的电路。

公开(公告)号：US20090185409A1

公开(公告)日：2009-07-23

申请号：US12017404

申请日：2008-01-22

申请人： Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

发明人： Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/412

摘要： A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.

摘要翻译： 存储器电路包括多个位线结构（每个都包括真和互补位线），与多个位线结构相交以形成多个单元位置的多个字线结构和位于该位线的多个单元 多个单元位置。 每个单元包括逻辑存储元件，选择性地将给定的一个真位线耦合到逻辑存储元件的第一存取晶体管和选择性地将对应的给定的一个互补位线耦合到逻辑存储器的第二存取晶体管 元件。 第一和第二存取晶体管中的一个或两个被配置为具有不对称电流特性，以实现READ和WRITE边缘的独立增强。 还包括在6-T范围内的是包括在机器可读介质中的一个或多个设计结构，包括如本文所述的电路。

公开(公告)号：US07274217B2

公开(公告)日：2007-09-25

申请号：US11100883

申请日：2005-04-07

申请人： Ching-Te Kent Chuang ,  Koushik Kumar Das ,  Shih-Hsien Lo

发明人： Ching-Te Kent Chuang ,  Koushik Kumar Das ,  Shih-Hsien Lo

IPC分类号： H01L23/62 ,  H03K19/094

CPC分类号： H03K19/0016 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance penalty associated with conventional PFET headers. A first embodiment of the invention provides a HOT-B high-VTH thick oxide bulk PFET header scheme. This header scheme can be expanded by application of a positive gate bias VPOS (VPOS>VDD) to the HOT-B PFET header during standby mode and a negative gate bias VNEG (VNEG

摘要翻译： 公开了结合MTCMOS和混合定向技术的CMOS电路设计，以实现高性能和低待机泄漏功率的双重目标。 本发明利用HOT技术中的厚氧化物高VTH PFET集线器的新型组合与各种栅极和体偏置方案，以显着降低与常规PFET集管相关的性能损失。 本发明的第一实施例提供了一种HOT-B高VTH厚氧化物体PFET头方案。 可以通过在待机模式期间将正栅极偏置VPOS（VPOS> VDD）施加到HOT-B PFET头并且在活动模式下使用负栅极偏置VNEG（VNEG

公开(公告)号：US20060226493A1

公开(公告)日：2006-10-12

申请号：US11100883

申请日：2005-04-07

申请人： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo

发明人： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo

IPC分类号： H01L29/94

CPC分类号： H03K19/0016 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance penalty associated with conventional PFET headers. A first embodiment of the invention provides a HOT-B high-VTH thick oxide bulk PFET header scheme. This header scheme can be expanded by application of a positive gate bias VPOS (VPOS>VDD) to the HOT-B PFET header during standby mode and a negative gate bias VNEG (VNEG

摘要翻译： 公开了结合MTCMOS和混合定向技术的CMOS电路设计，以实现高性能和低待机泄漏功率的双重目标。 本发明利用HOT技术中的厚氧化物高VTH PFET集线器的新型组合与各种栅极和体偏置方案，以显着降低与常规PFET集管相关的性能损失。 本发明的第一实施例提供了一种HOT-B高VTH厚氧化物体PFET头方案。 可以通过在待机模式期间将正栅极偏置VPOS（VPOS> VDD）施加到HOT-B PFET头并且在活动模式下使用负栅极偏置VNEG（VNEG

公开(公告)号：US20130260525A1

公开(公告)日：2013-10-03

申请号：US13438437

申请日：2012-04-03

申请人： Leland Chang ,  Chung-Hsun Lin ,  Shih-Hsien Lo ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Chung-Hsun Lin ,  Shih-Hsien Lo ,  Jeffrey W. Sleight

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/6659

摘要： A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length.

摘要翻译： 一种静态随机存取存储器制造方法包括在衬底上形成栅极堆叠，在栅极叠层附近形成隔离间隔物，隔离间隔物和栅极叠层具有栅极长度，形成与栅极堆叠相邻的源极和漏极区域，其产生有效的 栅极长度，其中源极和漏极区域由改变栅极长度和有效栅极长度之间的差异的低延伸剂量注入形成。

公开(公告)号：US08822295B2

公开(公告)日：2014-09-02

申请号：US13438437

申请日：2012-04-03

申请人： Leland Chang ,  Chung-Hsun Lin ,  Shih-Hsien Lo ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Chung-Hsun Lin ,  Shih-Hsien Lo ,  Jeffrey W. Sleight

IPC分类号： H01L29/78

CPC分类号： H01L29/7833 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/6659

摘要： A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length.

摘要翻译： 一种静态随机存取存储器制造方法包括在衬底上形成栅极堆叠，在栅极叠层附近形成隔离间隔物，隔离间隔物和栅极叠层具有栅极长度，形成与栅极堆叠相邻的源极和漏极区域，其产生有效的 栅极长度，其中源极和漏极区域由改变栅极长度和有效栅极长度之间的差异的低延伸剂量注入形成。

公开(公告)号：US08381156B1

公开(公告)日：2013-02-19

申请号：US13217381

申请日：2011-08-25

申请人： Michael P. Beakes ,  Shih-Hsien Lo ,  Michael R. Scheuermann ,  Matthew R. Wordeman

发明人： Michael P. Beakes ,  Shih-Hsien Lo ,  Michael R. Scheuermann ,  Matthew R. Wordeman

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/40 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.

摘要翻译： 提供了一种用于验证要组合成3D芯片堆栈的两个或更多个层的层间连通性的方法。 两个或更多个层中的每一个具有包括主动3D元素，机械3D元素和虚拟3D元素的3D元素。 该方法包括相对于至少3D元件在两个或更多个层中的每一个上执行相应的2D布局，以相对于示意图验证，以便当两个或更多个层随后被堆叠到3D元素中时，预先确保在3D元件之间不存在短路 3D芯片堆栈。 该方法还包括检查3D芯片堆叠中每个相邻层之间的层间互连性。

公开(公告)号：US20070018248A1

公开(公告)日：2007-01-25

申请号：US11184244

申请日：2005-07-19

申请人： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo ,  Jeffrey Sleight

发明人： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo ,  Jeffrey Sleight

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092

摘要： Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably in a high-performance, high density UTSOI; while the headers or footers are made of bulk epitaxial CMOS devices, with or without an adaptive well-biasing scheme. The logic transistors are based on (100) SOI devices or super HOT, the header devices are in bulk (100) or (110) pFETs with or without an adaptive well biasing scheme, and the footer devices are in bulk (100) NFET with or without an adaptive well biasing scheme.

摘要翻译： 公开了一种多阈值CMOS电路和一种设计这种电路的方法。 优选实施例组合MTCMOS方案和混合SOI外延CMOS结构。 通常，逻辑晶体管（nFET和pFET都）放置在SOI中，优选地以高性能，高密度的UTSOI; 而集管或页脚由大量外延CMOS器件制成，具有或不具有自适应阱偏置方案。 逻辑晶体管基于（100）SOI器件或超级HOT，头部器件处于具有或不具有自适应阱偏置方案的体（100）或（110）pFET中，并且脚踏器件处于本体（100）NFET中 或没有自适应井偏置方案。