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    High performance semiconductor devices and their manufacture
    5.
    发明授权
    High performance semiconductor devices and their manufacture 失效
    高性能半导体器件及其制造

    公开(公告)号：US5242854A

    公开(公告)日：1993-09-07

    申请号：US879650

    申请日：1992-05-07

    申请人： Alan G. Solheim ,  Christopher S. Blair ,  Vida Ilderem ,  Ali A. Iranmanesh

    发明人： Alan G. Solheim ,  Christopher S. Blair ,  Vida Ilderem ,  Ali A. Iranmanesh

    IPC分类号： H01L21/285 ,  H01L21/32 ,  H01L21/331 ,  H01L21/762 ,  H01L29/732

    CPC分类号： H01L29/6628 ,  H01L21/28525 ,  H01L21/32 ,  H01L21/76205 ,  H01L29/732

    摘要： A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for submicron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

    摘要翻译： 高性能双极晶体管及其制造方法。 通过在外部基极的单晶区域中形成的自对准硅化物来降低基极电阻，从而消除多晶硅到单晶接触电阻以及分流单晶非本征基极区域的电阻。 在硅化物形成之前，选择性地去除来自多晶硅局部互连的侧壁的氧化物。 因此，多晶硅互连层的选定侧壁也变成硅化物。 这导致互连电阻的显着降低，特别是对于亚微米几何形状。 还公开了用于形成场氧化物区域和用于形成双极晶体管的基极区域的改进的技术。

    Cell based array having compute/drive ratios of N:1
    6.
    发明授权
    Cell based array having compute/drive ratios of N:1 失效
    计算/驱动比为N：1的基于单元的阵列

    公开(公告)号：US06177709B1

    公开(公告)日：2001-01-23

    申请号：US08885148

    申请日：1997-06-30

    申请人： Ali A. Iranmanesh

    发明人： Ali A. Iranmanesh

    IPC分类号： H01L2711

    CPC分类号： H01L27/11807

    摘要： Method and apparatus are disclosed for a low power, high density cell based array structure that permits implementation of designs having compute/drive cell ratios of N:1. The improved performance is provided in part by relocating the substrate and well taps within the compute cell, and in at least some instances by removing the well tap from the drive cell. Further, an extra routing track may be provided by not sharing source/drain areas of adjacent drive cells.

    摘要翻译： 公开了用于低功率，高密度的基于单元的阵列结构的方法和装置，其允许实现具有N：1的计算/驱动单元比率的设计。 改进的性能部分地通过将基板和阱抽头重新定位在计算单元内，并且在至少一些情况下通过从驱动单元去除阱抽头来提供。 此外，可以通过不共享相邻驱动单元的源极/漏极区域来提供额外的路由轨道。

    Transistors having bases with different shape top surfaces
    8.
    发明授权
    Transistors having bases with different shape top surfaces 失效
    晶体管具有不同形状顶表面的基底

    公开(公告)号：US5389552A

    公开(公告)日：1995-02-14

    申请号：US10919

    申请日：1993-01-29

    申请人： Ali A. Iranmanesh

    发明人： Ali A. Iranmanesh

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L21/265

    CPC分类号： H01L29/66272 ,  H01L29/0692 ,  H01L29/0804 ,  Y10S148/01 ,  Y10S148/011

    摘要： A bipolar transistor is provided in which the emitters do not traverse the base but terminate inside the top surface of the base. Each emitter is L-shaped in some embodiments. The base top surface has a polygonal or circular outer boundary. The transistor has a long emitter perimeter available for base current flow and more than two emitter sides (e.g., five sides) available for base current flow. Further, the transistor has a large ratio of the emitter area to the base area. Consequently, the transistor has low noise, high gain, high frequency range, and a small size.

    摘要翻译： 提供了一种双极晶体管，其中发射体不穿过基底，而是终止在基底的顶表面内。 在一些实施例中，每个发射器是L形的。 基底表面具有多边形或圆形外边界。 晶体管具有可用于基极电流的长的发射极周边和可用于基极电流的多于两个发射极侧（例如，五个侧面）。 此外，晶体管的发射极面积与基极面积的比率大。 因此，晶体管具有低噪声，高增益，高频范围和小尺寸。

    Method of forming an antifuse in an integrated circuit
    9.
    发明授权
    Method of forming an antifuse in an integrated circuit 失效
    在集成电路中形成反熔丝的方法

    公开(公告)号：US5627098A

    公开(公告)日：1997-05-06

    申请号：US592039

    申请日：1996-01-26

    申请人： Ali A. Iranmanesh

    发明人： Ali A. Iranmanesh

    IPC分类号： H01L23/525 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L23/5252 ,  H01L2924/0002

    摘要： An antifuse structure in an integrated circuit including a first interconnection line, a second interconnection line formed over the first interconnection line, and a plurality of programming layers between the first and second interconnection lines. Each pair of programming layers has a metal layer therebetween which dissolves with the programming layers to form a conducting link during the programming of such antifuse structure. Such antifuse structure may also include a conductive plug between the programming layers and the second interconnection line.

    摘要翻译： 集成电路中的反熔丝结构，包括第一互连线，形成在第一互连线上的第二互连线，以及在第一和第二互连线之间的多个编程层。 每对编程层之间具有金属层，其间在编程这种反熔丝结构期间与编程层一起形成导电连接。 这种反熔丝结构还可以包括编程层和第二互连线之间的导电插塞。

    Apparatus for improvement of interconnection capacitance
    10.
    发明授权
    Apparatus for improvement of interconnection capacitance 失效
    用于改善互连电容的装置

    公开(公告)号：US5262672A

    公开(公告)日：1993-11-16

    申请号：US799516

    申请日：1991-11-27

    申请人： Ali A. Iranmanesh

    发明人： Ali A. Iranmanesh

    IPC分类号： H01L23/522 ,  H01L29/72 ,  H01L29/34

    CPC分类号： H01L23/5222 ,  H01L2924/0002

    摘要： A method and apparatus for reducing interconnection capacitance. A lightly doped buried layer is provided in or on a substrate below a field oxide region. The capacitance of an interconnect on the field oxide is significantly reduced by the lightly doped buried layer. When using a p-type substrate, the lightly doped buried layer may, for example, be a lightly doped (10.sup.13 /cm.sup.3) n-type region. Junction capacitance of, for example, a bipolar transistor is also reduced.

    摘要翻译： 一种减少互连电容的方法和装置。 轻掺杂掩埋层设置在场氧化物区域下方的衬底中或衬底上。 通过轻掺杂掩埋层，场氧化物上的互连的电容显着降低。 当使用p型衬底时，轻掺杂掩埋层可以例如是轻掺杂（1013 / cm3）的n型区域。 例如双极晶体管的结电容也降低。