公开(公告)号：US20120159008A1

公开(公告)日：2012-06-21

申请号：US13332545

申请日：2011-12-21

申请人： Sung Geun Park ,  Chul Joon Choi ,  Tae-Geuk Kim

发明人： Sung Geun Park ,  Chul Joon Choi ,  Tae-Geuk Kim

IPC分类号： G06F3/00

CPC分类号： G06F13/387

摘要： A method of operating a multi-interface memory card including a first interface supporting a universal serial bus (USB) data transfer protocol and the second interface supporting an inter-chip USB (IC-USB) data transfer protocol includes; selecting either the first interface or the second interface to facilitate data communication between the multi-interface memory card and a host connected to the multi-interface memory card via a USB connection by comparing a level of a power-on voltage received from the host with a reference voltage level, and thereafter determining whether a reset signal has been received from the host.

摘要翻译： 一种操作包括支持通用串行总线（USB）数据传输协议的第一接口和支持片上USB（IC-USB）数据传输协议的第二接口）的多接口存储卡的方法包括： 选择第一接口或第二接口，以通过将从主机接收到的通电电压的电平与来自主机的电源电压进行比较来促进多接口存储卡与连接到多接口存储卡的主机之间的数据通信， 参考电压电平，然后确定是否已经从主机接收到复位信号。

公开(公告)号：US06383877B1

公开(公告)日：2002-05-07

申请号：US09573268

申请日：2000-05-18

申请人： Dong-ho Ahn ,  Ja-hum Ku ,  Chul-sung Kim ,  Jae-yoon Yoo ,  Sug-hun Hong ,  Chul-joon Choi

发明人： Dong-ho Ahn ,  Ja-hum Ku ,  Chul-sung Kim ,  Jae-yoon Yoo ,  Sug-hun Hong ,  Chul-joon Choi

IPC分类号： H01L21425

CPC分类号： H01L29/66598 ,  H01L21/28518 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66636

摘要： A method of forming a T-shaped isolation layer, a method of forming an elevated salicide source/drain region using the same, and a semiconductor device having the T-shaped isolation layer are provided. In the method of forming the T-shaped isolation layer, an isolation layer having a narrow trench region in the lower portion thereof and a wide trench region in the upper portion thereof is formed on a semiconductor substrate. Also, in the method of forming the elevated salicide source/drain region, the method of forming the T-shaped isolation layer is used. In particular, conductive impurities can also be implanted into the lower portion of the wide trench region which constitutes the head of the T-shaped isolation layer and is extended to both sides from the upper end of the narrow trench region by controlling the depth of the wide trench region in an ion implantation step for forming the source/drain region.

摘要翻译： 提供形成T形隔离层的方法，使用该方法形成提高的自对准硅化物源极/漏极区域的方法以及具有T形隔离层的半导体器件。 在形成T形隔离层的方法中，在半导体衬底上形成在其下部具有窄沟槽区和其上部宽沟槽区的隔离层。 此外，在形成升高的自对准硅化物源极/漏极区域的方法中，使用形成T形隔离层的方法。 特别地，也可以将导电杂质注入构成T形隔离层的头部的宽沟槽区域的下部，并且通过控制该窄沟槽区域的深度而从窄沟槽区域的上端延伸到两侧 在用于形成源极/漏极区域的离子注入步骤中形成宽沟槽区域。

公开(公告)号：US08769160B2

公开(公告)日：2014-07-01

申请号：US13332545

申请日：2011-12-21

申请人： Sung Geun Park ,  Chul Joon Choi ,  Tae-Geuk Kim

发明人： Sung Geun Park ,  Chul Joon Choi ,  Tae-Geuk Kim

IPC分类号： G06F3/00 ,  G06F13/26

CPC分类号： G06F13/387

摘要： A method of operating a multi-interface memory card including a first interface supporting a universal serial bus (USB) data transfer protocol and the second interface supporting an inter-chip USB (IC-USB) data transfer protocol includes; selecting either the first interface or the second interface to facilitate data communication between the multi-interface memory card and a host connected to the multi-interface memory card via a USB connection by comparing a level of a power-on voltage received from the host with a reference voltage level, and thereafter determining whether a reset signal has been received from the host.

摘要翻译： 一种操作包括支持通用串行总线（USB）数据传输协议的第一接口和支持片上USB（IC-USB）数据传输协议的第二接口）的多接口存储卡的方法包括： 选择第一接口或第二接口，以通过将从主机接收到的通电电压的电平与来自主机的电源电压进行比较来促进多接口存储卡与连接到多接口存储卡的主机之间的数据通信， 参考电压电平，然后确定是否已经从主机接收到复位信号。

公开(公告)号：US08145935B2

公开(公告)日：2012-03-27

申请号：US12188820

申请日：2008-08-08

申请人： Sung Geun Park ,  Chul Joon Choi ,  Hyuk Jun Sung ,  Byung Yoon Kang

发明人： Sung Geun Park ,  Chul Joon Choi ,  Hyuk Jun Sung ,  Byung Yoon Kang

IPC分类号： G06F1/041

CPC分类号： H04L7/08 ,  G06F1/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/085

摘要： A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.

摘要翻译： 时钟信号发生器可以包括被配置为产生时钟信号的时钟信号产生单元。 时钟信号控制单元被配置为在参考时间期间对时钟信号的脉冲数进行计数，并且将脉冲数与参考值进行比较以提供比较结果，并且基于比较结果生成控制信号 其中时钟信号产生单元基于控制信号增加或减少时钟信号的脉冲数。

公开(公告)号：US20120005488A1

公开(公告)日：2012-01-05

申请号：US13236897

申请日：2011-09-20

申请人： Joong-Chul YOON ,  Seong-Hyun KIM ,  Sung-Hyun KIM ,  Sang-Bum KIM ,  Sang-Wook KANG ,  Chul-Joon CHOI ,  Jong-Sang CHOI ,  Keon-Han SOHN ,  Byung-Yoon KANG

发明人： Joong-Chul YOON ,  Seong-Hyun KIM ,  Sung-Hyun KIM ,  Sang-Bum KIM ,  Sang-Wook KANG ,  Chul-Joon CHOI ,  Jong-Sang CHOI ,  Keon-Han SOHN ,  Byung-Yoon KANG

IPC分类号： G06F12/14

CPC分类号： H04L9/0625 ,  H04L9/0877 ,  H04L2209/34

摘要： An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

摘要翻译： 一种加密处理器，用于将加密数据存储在存储卡的存储器芯片中，包括用于响应于第一信号顺序地输出m位数据的FIFO存储器和用于产生m位加密密钥的加密密钥产生器（m为 正整数），并响应于第三信号顺序输出键。 逻辑运算符在数据写入操作期间利用来自加密密钥生成器的密钥从FIFO存储器的数据执行逻辑运算，以顺序加密数据。 在数据读取操作期间，逻辑运算符对从加密密钥生成器输出的密钥从存储器接口接收的加密数据执行逻辑运算，以便对加密的数据进行顺序解码。 第二个信号与写入命令或读取命令之一同时生成。

公开(公告)号：US08054972B2

公开(公告)日：2011-11-08

申请号：US11853041

申请日：2007-09-11

申请人： Joong-Chul Yoon ,  Seong-Hyun Kim ,  Sung-hyun Kim ,  Sang-Bum Kim ,  Sang-Wook Kang ,  Chul-Joon Choi ,  Jong-Sang Choi ,  Koon-Han Sohn ,  Byung-Yoon Kang

发明人： Joong-Chul Yoon ,  Seong-Hyun Kim ,  Sung-hyun Kim ,  Sang-Bum Kim ,  Sang-Wook Kang ,  Chul-Joon Choi ,  Jong-Sang Choi ,  Koon-Han Sohn ,  Byung-Yoon Kang

IPC分类号： H04K1/00

CPC分类号： H04L9/0625 ,  H04L9/0877 ,  H04L2209/34

摘要： An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

摘要翻译： 一种加密处理器，用于将加密数据存储在存储卡的存储器芯片中，包括用于响应于第一信号顺序地输出m位数据的FIFO存储器和用于产生m位加密密钥的加密密钥产生器（m为 正整数），并响应于第三信号顺序输出键。 逻辑运算符在数据写入操作期间利用来自加密密钥生成器的密钥从FIFO存储器的数据执行逻辑运算，以顺序加密数据。 在数据读取操作期间，逻辑运算符对从加密密钥生成器输出的密钥从存储器接口接收的加密数据执行逻辑运算，以便对加密的数据进行顺序解码。 第二个信号与写入命令或读取命令之一同时生成。

公开(公告)号：US20100281187A1

公开(公告)日：2010-11-04

申请号：US12837431

申请日：2010-07-15

申请人： Sang-Bum Kim ,  Sang-Wook Kang ,  Seong-Hyun Kim ,  Chul-Joon Choi ,  Jong-Sang Choi

发明人： Sang-Bum Kim ,  Sang-Wook Kang ,  Seong-Hyun Kim ,  Chul-Joon Choi ,  Jong-Sang Choi

IPC分类号： G06F3/00 ,  G06F13/42

CPC分类号： G06F13/385

摘要： An electronic device includes a universal serial bus (USB) interface therein. This USB interface is configured to support at least first and second different USB interface standards. These different interface standards are selected by the electronic device in response to comparing a voltage level of a signal provided to said USB interface relative to a reference voltage generated within the electronic device. The signal provided to the USB may be a power supply signal, the first USB standard may be a USB 2.0 interface standard and the second USB standard may be an inter-chip USB interface standard.

摘要翻译： 电子设备包括其中的通用串行总线（USB）接口。 该USB接口被配置为支持至少第一和第二不同的USB接口标准。 响应于比较提供给所述USB接口的信号的电压电平相对于在电子设备内产生的参考电压，电子设备选择这些不同的接口标准。 提供给USB的信号可以是电源信号，第一USB标准可以是USB 2.0接口标准，第二USB标准可以是芯片间的USB接口标准。

公开(公告)号：US20090049326A1

公开(公告)日：2009-02-19

申请号：US12188820

申请日：2008-08-08

申请人： Sung Geun Park ,  Chul Joon Choi ,  Hyuk Jun Sung ,  Byung Yoon Kang

发明人： Sung Geun Park ,  Chul Joon Choi ,  Hyuk Jun Sung ,  Byung Yoon Kang

IPC分类号： G06F1/04

CPC分类号： H04L7/08 ,  G06F1/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/085

摘要： A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.

摘要翻译： 时钟信号发生器可以包括被配置为产生时钟信号的时钟信号生成单元。 时钟信号控制单元被配置为在参考时间期间对时钟信号的脉冲数进行计数，并且将脉冲数与参考值进行比较以提供比较结果，并且基于比较结果生成控制信号 其中时钟信号产生单元基于控制信号增加或减少时钟信号的脉冲数。

公开(公告)号：US20080276015A1

公开(公告)日：2008-11-06

申请号：US12175155

申请日：2008-07-17

申请人： Seong-Hyun Kim ,  Sang-Bum Kim ,  Joong-Chul Yoon ,  Sang-Wook Kang ,  Jong-Sang Choi ,  Sung-Hyun Kim ,  Chul-Joon Choi

发明人： Seong-Hyun Kim ,  Sang-Bum Kim ,  Joong-Chul Yoon ,  Sang-Wook Kang ,  Jong-Sang Choi ,  Sung-Hyun Kim ,  Chul-Joon Choi

IPC分类号： G06F3/00

CPC分类号： G06K7/0008 ,  G06K7/10297 ,  G06K19/07

摘要： The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

摘要翻译： 本发明提供一种集成电路芯片，其包括处理器; 接触垫单元，其通过多个接触垫连接到主机; 主机接口检测器，包括至少一个上拉电阻器和一个下拉电阻器，用于选择性地将上拉电阻器和下拉电阻器连接到接触焊盘单元以检测主机接口状态; 以及包括多个接口协议的接口单元，用于使用所述多个接触焊盘中的一部分或全部与所述主机进行通信，其中所述处理器从所述主机接口检测器接收所述主机的状态，识别所述主机的协议 关于主机的接收状态，并控制接口单元，以便启用用于与主机通信的接口协议。

公开(公告)号：US20080013396A1

公开(公告)日：2008-01-17

申请号：US11798469

申请日：2007-05-14

申请人： Jong-Sang Choi ,  Seong-Hyun Kim ,  Sung-Hyun Kim ,  Sang-Bum Kim ,  Joong-Chul Yoon ,  Sang-Wook Kang ,  Chul-Joon Choi

发明人： Jong-Sang Choi ,  Seong-Hyun Kim ,  Sung-Hyun Kim ,  Sang-Bum Kim ,  Joong-Chul Yoon ,  Sang-Wook Kang ,  Chul-Joon Choi

IPC分类号： G11C5/14

CPC分类号： G06K19/077 ,  G06K19/07732

摘要： A method and apparatus for resetting a memory card having a plurality of interfaces and a plurality of function blocks, wherein each function block may be associated with a corresponding interface, may include detecting a reset signal for a selected interface of the plurality of interfaces, and interrupting a function block associated with the selected interface. When the selected interface is the only active interface, all function blocks in the memory card may be reset. If interfaces other than the selected interface are active, only the selected interface may be reset.

摘要翻译： 一种用于复位具有多个接口和多个功能块的存储卡的方法和装置，其中每个功能块可以与对应的接口相关联，可以包括检测所述多个接口中所选接口的复位信号，以及 中断与所选接口相关联的功能块。 当所选接口是唯一的活动接口时，存储卡中的所有功能块都可能被复位。 如果所选接口以外的接口处于活动状态，则只能选择接口。