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    Memory and manufacturing method thereof
    1.
    发明授权
    Memory and manufacturing method thereof 有权

    公开(公告)号：US08581327B2

    公开(公告)日：2013-11-12

    申请号：US12974093

    申请日：2010-12-21

    申请人： Erh-Kun Lai ,  Yen-Hao Shih ,  Ling-Wu Yang ,  Chun-Min Cheng

    发明人： Erh-Kun Lai ,  Yen-Hao Shih ,  Ling-Wu Yang ,  Chun-Min Cheng

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7923

    摘要： A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.

    MEMORY AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    MEMORY AND MANUFACTURING METHOD THEREOF 有权
    内存及其制造方法

    公开(公告)号：US20110089480A1

    公开(公告)日：2011-04-21

    申请号：US12974093

    申请日：2010-12-21

    申请人： Erh-Kun Lai ,  Yen-Hao Shih ,  Ling-Wu Yang ,  Chun-Min Cheng

    发明人： Erh-Kun Lai ,  Yen-Hao Shih ,  Ling-Wu Yang ,  Chun-Min Cheng

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7923

    摘要： A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.

    摘要翻译： 提供具有隔离双存储单元的存储器。 第一隔离壁和第二隔离壁分别设置在基板上的源极和漏极之间。 隔离底层和多晶硅层有序地设置在第一和第二隔离壁之间的衬底上。 第一电荷存储结构和第一栅极有序地设置在第一隔离壁和源极之间的衬底上。 第二电荷存储结构和第二栅极有序地设置在第二隔离壁和漏极之间的衬底上。 布置在多晶硅层上的字线，第一栅极，第二栅极，第一隔离壁和第二隔离壁电连接到第一栅极，第二栅极和多晶硅层。

    Memory and manufacturing method thereof
    5.
    发明申请
    Memory and manufacturing method thereof 有权
    其记忆及其制造方法

    公开(公告)号：US20090108331A1

    公开(公告)日：2009-04-30

    申请号：US11979101

    申请日：2007-10-31

    申请人： Erh-Kun Lai ,  Yen-Hao Shih ,  Ling-Wu Yang ,  Chun-Min Cheng

    发明人： Erh-Kun Lai ,  Yen-Hao Shih ,  Ling-Wu Yang ,  Chun-Min Cheng

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7923

    摘要： A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.

    摘要翻译： 提供具有隔离双存储单元的存储器。 第一隔离壁和第二隔离壁分别设置在基板上的源极和漏极之间。 隔离底层和多晶硅层有序地设置在第一和第二隔离壁之间的衬底上。 第一电荷存储结构和第一栅极有序地设置在第一隔离壁和源极之间的衬底上。 第二电荷存储结构和第二栅极有序地设置在第二隔离壁和漏极之间的衬底上。 布置在多晶硅层上的字线，第一栅极，第二栅极，第一隔离壁和第二隔离壁电连接到第一栅极，第二栅极和多晶硅层。

    Semiconductor device formation
    6.
    发明授权
    Semiconductor device formation 有权
    半导体器件形成

    公开(公告)号：US08872260B2

    公开(公告)日：2014-10-28

    申请号：US13489227

    申请日：2012-06-05

    申请人： Jung-Yi Guo ,  Chun-Min Cheng

    发明人： Jung-Yi Guo ,  Chun-Min Cheng

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76237

    摘要： An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches.

    摘要翻译： 用于制造具有基本上V形轮廓的浅沟槽隔离（STI）沟槽的半导体结构的装置和方法，即，顶部之间的距离大于浅沟槽隔离（STI）结构的底部之间的距离 邻近沟槽的侧壁提供基本上无缝且基本上无空隙的栅极结构。 半导体结构通过将注入物质注入到侧壁中形成，这允许侧壁的顶部以比底部部分更高的速率被蚀刻掉，从而形成基本上V形的轮廓。 并且由于朝向沟槽的顶部的更宽的开口，基本上V形的轮廓允许随后的器件层更容易且平滑地填充在V形沟槽中。

    SEMICONDUCTOR DEVICE FORMATION
    7.
    发明申请
    SEMICONDUCTOR DEVICE FORMATION 有权
    半导体器件形成

    公开(公告)号：US20130320484A1

    公开(公告)日：2013-12-05

    申请号：US13489227

    申请日：2012-06-05

    申请人： JUNG-YI GUO ,  CHUN-MIN CHENG

    发明人： JUNG-YI GUO ,  CHUN-MIN CHENG

    IPC分类号： H01L29/00 ,  H01L21/76

    CPC分类号： H01L21/76237

    摘要： An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches.

    摘要翻译： 用于制造具有基本上V形轮廓的浅沟槽隔离（STI）沟槽的半导体结构的装置和方法，即，顶部之间的距离大于浅沟槽隔离（STI）结构的底部之间的距离 邻近沟槽的侧壁提供基本上无缝且基本上无空隙的栅极结构。 半导体结构通过将注入物质注入到侧壁中形成，这允许侧壁的顶部以比底部部分更高的速率被蚀刻掉，从而形成基本上V形的轮廓。 并且由于朝向沟槽的顶部的更宽的开口，基本上V形的轮廓允许随后的器件层更容易且平滑地填充在V形沟槽中。

    Memory and manufacturing method thereof
    10.
    发明授权
    Memory and manufacturing method thereof 有权
    其记忆及其制造方法

    公开(公告)号：US07879706B2

    公开(公告)日：2011-02-01

    申请号：US11979101

    申请日：2007-10-31

    申请人： Erh-Kun Lai ,  Yen-Hao Shih ,  Ling-Wu Yang ,  Chun-Min Cheng

    发明人： Erh-Kun Lai ,  Yen-Hao Shih ,  Ling-Wu Yang ,  Chun-Min Cheng

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7923

    摘要： A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.

    摘要翻译： 提供具有隔离双存储单元的存储器。 第一隔离壁和第二隔离壁分别设置在基板上的源极和漏极之间。 隔离底层和多晶硅层有序地设置在第一和第二隔离壁之间的衬底上。 第一电荷存储结构和第一栅极有序地设置在第一隔离壁和源极之间的衬底上。 第二电荷存储结构和第二栅极有序地设置在第二隔离壁和漏极之间的衬底上。 布置在多晶硅层上的字线，第一栅极，第二栅极，第一隔离壁和第二隔离壁电连接到第一栅极，第二栅极和多晶硅层。