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    Two Bits Per Cell Non-Volatile Memory Architecture
    2.
    发明申请
    Two Bits Per Cell Non-Volatile Memory Architecture 失效
    每个单元非易失性存储器架构的两个位

    公开(公告)号：US20100208530A1

    公开(公告)日：2010-08-19

    申请号：US12370718

    申请日：2009-02-13

    申请人： Chee T. Chua ,  Kameswara K. Rao ,  Vithal R. Rao ,  Jawji Chen ,  Da-Guang Yu ,  J. Eric Ruetz ,  Stephen Fung

    发明人： Chee T. Chua ,  Kameswara K. Rao ,  Vithal R. Rao ,  Jawji Chen ,  Da-Guang Yu ,  J. Eric Ruetz ,  Stephen Fung

    IPC分类号： G11C7/00

    CPC分类号： G11C16/0441

    摘要： A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.

    摘要翻译： 用于保存单个二进制值的存储器电路。 第一位单元保持逻辑高值和逻辑低值中的一个，并且第二位单元也保持逻辑高值和逻辑低值中的一个。 提供电路，用于当存储器电路中的二进制值为逻辑高值时，将逻辑高值放置在第一位单元中，并且提供电路用于当第二位单元中的二进制值 存储器电路将成为逻辑低电平值。 以这种方式，存储器电路内存在逻辑高值，存储器电路内的单个二进制值是逻辑高值还是逻辑低值。 二进制值的两个值之间的差异是两个位单元中哪一个保持逻辑高值。 因此，可以在不使用读出放大器的情况下感测该存储器电路。

    Two bits per cell non-volatile memory architecture
    4.
    发明授权
    Two bits per cell non-volatile memory architecture 失效
    每个单元两位非易失性存储器架构

    公开(公告)号：US08081521B2

    公开(公告)日：2011-12-20

    申请号：US12370718

    申请日：2009-02-13

    申请人： Chee T. Chua ,  Kameswara K. Rao ,  Vithal R. Rao ,  Jawji Chen ,  Da-Guang Yu ,  J. Eric Ruetz ,  Stephen Fung

    发明人： Chee T. Chua ,  Kameswara K. Rao ,  Vithal R. Rao ,  Jawji Chen ,  Da-Guang Yu ,  J. Eric Ruetz ,  Stephen Fung

    IPC分类号： G11C7/00

    CPC分类号： G11C16/0441

    摘要： A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.

    摘要翻译： 用于保存单个二进制值的存储器电路。 第一位单元保持逻辑高值和逻辑低值中的一个，并且第二位单元也保持逻辑高值和逻辑低值中的一个。 提供电路，用于当存储器电路中的二进制值为逻辑高值时，将逻辑高值放置在第一位单元中，并且提供电路用于当第二位单元中的二进制值 存储器电路将成为逻辑低电平值。 以这种方式，存储器电路内存在逻辑高值，存储器电路内的单个二进制值是逻辑高值还是逻辑低值。 二进制值的两个值之间的差异是两个位单元中哪一个保持逻辑高值。 因此，可以在不使用读出放大器的情况下感测该存储器电路。

    Constant reference cell current generator for non-volatile memories
    5.
    发明授权
    Constant reference cell current generator for non-volatile memories 失效
    用于非易失性存储器的恒定参考电池电流发生器

    公开(公告)号：US07944281B2

    公开(公告)日：2011-05-17

    申请号：US12334338

    申请日：2008-12-12

    申请人： Da-Guang Yu ,  Vithal Rao

    发明人： Da-Guang Yu ,  Vithal Rao

    IPC分类号： G05F1/12

    CPC分类号： G05F3/24

    摘要： A reference current generation circuit generates a first branch current that varies by a first percentage in response to variations in a first supply voltage and variations in transistor threshold voltage. The first branch current is mirrored to create a corresponding second branch current. A first portion (sub-current) of the second branch current is supplied through a first transistor, which exhibits the transistor threshold voltage wherein the first sub-current varies by a second percentage in response to the variations in the first supply voltage and variations in transistor threshold voltage, wherein the second percentage is greater than the first percentage. A second portion (sub-current) of the second branch current is supplied through a second transistor. The second portion of the second branch current is mirrored to create a reference current (IREF).

    摘要翻译： 参考电流产生电路产生响应于第一电源电压的变化和晶体管阈值电压的变化而变化第一百分比的第一支路电流。 第一个分支电流被镜像以产生相应的第二分支电流。 通过第一晶体管提供第二分支电流的第一部分（子电流），第一晶体管呈现晶体管阈值电压，其中第一子电流响应于第一电源电压的变化而变化第二百分比， 晶体管阈值电压，其中第二百分比大于第一百分比。 第二分支电流的第二部分（子电流）通过第二晶体管提供。 第二分支电流的第二部分被镜像以产生参考电流（IREF）。

    Constant Reference Cell Current Generator For Non-Volatile Memories
    6.
    发明申请
    Constant Reference Cell Current Generator For Non-Volatile Memories 失效
    用于非易失性存储器的恒定参考电池电流发生器

    公开(公告)号：US20100148855A1

    公开(公告)日：2010-06-17

    申请号：US12334338

    申请日：2008-12-12

    申请人： Da-Guang Yu ,  Vithal Rao

    发明人： Da-Guang Yu ,  Vithal Rao

    IPC分类号： G05F1/10

    CPC分类号： G05F3/24

    摘要： A reference current generation circuit generates a first branch current that varies by a first percentage in response to variations in a first supply voltage and variations in transistor threshold voltage. The first branch current is mirrored to create a corresponding second branch current. A first portion (sub-current) of the second branch current is supplied through a first transistor, which exhibits the transistor threshold voltage wherein the first sub-current varies by a second percentage in response to the variations in the first supply voltage and variations in transistor threshold voltage, wherein the second percentage is greater than the first percentage. A second portion (sub-current) of the second branch current is supplied through a second transistor. The second portion of the second branch current is mirrored to create a reference current (IREF).

    摘要翻译： 参考电流产生电路产生响应于第一电源电压的变化和晶体管阈值电压的变化而变化第一百分比的第一支路电流。 第一个分支电流被镜像以产生相应的第二分支电流。 通过第一晶体管提供第二分支电流的第一部分（子电流），第一晶体管呈现晶体管阈值电压，其中第一子电流响应于第一电源电压的变化而变化第二百分比， 晶体管阈值电压，其中第二百分比大于第一百分比。 第二分支电流的第二部分（子电流）通过第二晶体管提供。 第二分支电流的第二部分被镜像以产生参考电流（IREF）。