公开(公告)号：US20080084768A1

公开(公告)日：2008-04-10

申请号：US11604692

申请日：2006-11-28

申请人： Dae-sik Park ,  Jin-yub Lee

发明人： Dae-sik Park ,  Jin-yub Lee

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C11/34

CPC分类号： G11C7/1078 ,  G11C7/1087 ,  G11C11/5628

摘要： A memory device and method thereof are provided. The example memory device may include a first buffer receiving most significant bit (MSB) data and least significant bit (LSB) data to be stored within a memory cell, a second buffer loading stored LSB data stored from the memory cell and a data loader generating at least one load signal based upon logic levels of the received MSB data from the first buffer and the loaded LSB data from the memory cell, the at least one load signal controlling programming permissions for the memory cell. The example method may include receiving LSB data, storing the received LSB data within a memory cell, receiving MSB data, loading the LSB data from the programmed memory cell, generating at least one load signal based upon logic levels of the received MSB data and the loaded LSB data, the at least one load signal controlling programming permissions for the memory cell and storing the MSB data within the memory cell based on the at least one load signal.

摘要翻译： 提供了一种存储器件及其方法。 该示例性存储器件可以包括接收要存储在存储器单元内的最高有效位（MSB）数据和最低有效位（LSB））数据的第一缓冲器，第二缓冲器加载从存储器单元存储的存储的LSB数据，以及数据加载器生成 基于来自第一缓冲器的接收到的MSB数据的逻辑电平和来自存储器单元的加载的LSB数据的至少一个负载信号，所述至少一个负载信号控制对存储器单元的编程许可。 示例性方法可以包括接收LSB数据，将接收的LSB数据存储在存储器单元内，接收MSB数据，从编程的存储器单元加载LSB数据，基于所接收的MSB数据的逻辑电平产生至少一个负载信号，以及 所述至少一个负载信号控制所述存储器单元的编程许可，并且基于所述至少一个负载信号将所述MSB数据存储在所述存储器单元内。

公开(公告)号：US20070183221A1

公开(公告)日：2007-08-09

申请号：US11567895

申请日：2006-12-07

申请人： DAE-SIK PARK ,  Jin-Yub Lee

发明人： DAE-SIK PARK ,  Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/30 ,  G11C16/16

摘要： An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.

摘要翻译： 提供均匀擦除执行时间的擦除电压产生电路和具有该擦除执行时间的非易失性半导体存储器件，其中擦除电压产生电路包括高电压产生单元，电压电平检测单元，执行时间检查单元和 放电单元 高电压产生单元产生擦除电压。 电压电平检测单元检测擦除电压并产生电平检测信号。 当擦除电压达到目标电压时，电平检测信号被激活。 执行时间检查单元生成响应于从电平检测信号的激活而经过擦除执行时间而被激活的执行结束信号。 放电单元将擦除电压作为放电电压放电。 响应于执行结束信号的激活，高电压生成单元被禁用，并且放电单元响应于执行结束信号的激活而被使能。

公开(公告)号：US20130154101A1

公开(公告)日：2013-06-20

申请号：US13488246

申请日：2012-06-04

申请人： Dae Sik PARK

发明人： Dae Sik PARK

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L27/10855 ,  H01L21/76897

摘要： A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. The semiconductor device includes at least one bit line formed over a semiconductor substrate, a first storage node contact plug formed between the bit lines and coupled to an upper part of the semiconductor substrate, and a second storage node contact plug formed over the first storage node contact plug, wherein a width of a lower part of the second storage node contact plug is larger than a width of an upper part thereof.

公开(公告)号：US07773415B2

公开(公告)日：2010-08-10

申请号：US12292741

申请日：2008-11-25

申请人： Dae-Sik Park ,  Jin-Yub Lee

发明人： Dae-Sik Park ,  Jin-Yub Lee

IPC分类号： G11C16/26

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3427

摘要： A flash memory device includes a memory block including word lines arranged between a first selection line and a second selection line, the word lines being divided into a first group and a second group, a control logic configured to determine an activation order of the first and second selection lines and determine first and second read voltages to be supplied to unselected word lines, the control logic determining the activation order according to whether a selected word line belongs to the first group or the second group, and a row selection circuit configured to, during a read operation, drive the unselected word lines with the first and second read voltages, and activate the first and second selection lines, according to the control logic.

摘要翻译： 闪速存储器件包括存储块，其包括布置在第一选择线和第二选择线之间的字线，所述字线被分成第一组和第二组，控制逻辑被配置为确定第一和第二组的激活顺序， 第二选择线，并且确定要提供给未选字线的第一和第二读取电压，所述控制逻辑根据所选择的字线是否属于所述第一组或所述第二组来确定所述激活顺序;以及行选择电路， 在读取操作期间，利用第一和第二读取电压驱动未选择的字线，并根据控制逻辑激活第一和第二选择线。

公开(公告)号：US20100109731A1

公开(公告)日：2010-05-06

申请号：US12560943

申请日：2009-09-16

申请人： Jin-Ho Ko ,  Seng-Hyun Cho ,  Hyung-Chul Park ,  Dae-Sik Park

发明人： Jin-Ho Ko ,  Seng-Hyun Cho ,  Hyung-Chul Park ,  Dae-Sik Park

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： There is provided an apparatus for duty cycle correction. The apparatus for duty cycle correction comprises a moving sum unit performing a moving sum calculation with respect to the square-wave signal and outputting the moving sum signal subjected to moving sum calculation, a comparison unit comparing the moving sum signal with a predetermined threshold voltage, outputting a high signal or low signal, a mean value calculation unit calculating the mean value of an output signal outputted from the comparison unit, the output signal being included in a section having a period integer times greater than that of the square-wave signal, and a threshold voltage control unit comparing the mean value with a middle value, increasing the threshold voltage when the mean value is greater than the middle value, and decreasing the threshold voltage when the mean value is less than the middle value.

摘要翻译： 提供了一种用于占空比校正的装置。 用于占空比校正的装置包括：移动和单元，执行相对于方波信号的移动和计算，并输出经过移动和计算的移动和信号;比较单元，将移动和信号与预定阈值电压进行比较; 输出高信号或低信号的平均值计算单元，计算从比较单元输出的输出信号的平均值，输出信号被包括在具有比方波信号的整数倍的周期的区间中， 以及阈值电压控制单元，将平均值与中间值进行比较，当平均值大于中间值时增加阈值电压，并且当平均值小于中间值时降低阈值电压。

公开(公告)号：US20090101955A1

公开(公告)日：2009-04-23

申请号：US12341812

申请日：2008-12-22

申请人： Dae-Sik PARK

发明人： Dae-Sik PARK

IPC分类号： H01L27/108 ,  H01G9/025 ,  B05D5/12

CPC分类号： G11C13/0009 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0033 ,  G11C2213/79 ,  H01G4/33 ,  H01G9/22 ,  H01G11/02 ,  H01G11/26 ,  H01G11/30 ,  H01G11/56 ,  H01G11/84 ,  H01L27/10852 ,  H01L28/91 ,  H01L51/0595 ,  Y02E60/13

摘要： A molecular electronic device, and a method of fabricating the same, includes a first electrode having a plurality of prominences and depressions on which a plurality of molecules are self-assembled. Capacitance of a molecular electronic device used as a capacitor is increased by forming prominences and depressions on the surface of the first electrode thereby enabling more molecules to be self-assembled on the surface of the lower electrode.

摘要翻译： 分子电子器件及其制造方法包括具有多个突起和凹陷的第一电极，多个分子在其上自组装在该第一电极上。 通过在第一电极的表面上形成凸起和凹陷来增加用作电容器的分子电子器件的电容，从而使得能够在下电极的表面上自组装更多的分子。

公开(公告)号：US07486570B2

公开(公告)日：2009-02-03

申请号：US11320975

申请日：2005-12-30

申请人： Dae-Sik Park ,  Jin-Yub Lee ,  Seong-Kue Jo

发明人： Dae-Sik Park ,  Jin-Yub Lee ,  Seong-Kue Jo

IPC分类号： G11C7/10

CPC分类号： G11C16/10

摘要： Disclosed is a program method for a flash memory device which includes; storing data in a buffer memory and generating a high voltage as a word line voltage. When transmission of data to the buffer memory is complete, the program method simultaneously transfers data in the buffer memory to a page buffer circuit, and programs data in the page buffer circuit in a memory cell array according to the word line voltage.

摘要翻译： 公开了一种闪存器件的程序方法，包括： 将数据存储在缓冲存储器中并产生高电压作为字线电压。 当数据传送到缓冲存储器完成时，程序方法将缓冲存储器中的数据同时传送到页缓冲电路，并根据字线电压对存储单元阵列中的页缓冲电路中的数据进行编程。

公开(公告)号：US20080205142A1

公开(公告)日：2008-08-28

申请号：US12115827

申请日：2008-05-06

申请人： Dae-Sik Park ,  Jin-Yub Lee

发明人： Dae-Sik Park ,  Jin-Yub Lee

IPC分类号： G11C16/14

CPC分类号： G11C16/30 ,  G11C16/16

摘要： An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.

摘要翻译： 提供均匀擦除执行时间的擦除电压产生电路和具有该擦除执行时间的非易失性半导体存储器件，其中擦除电压产生电路包括一个电压电平检测单元，一个执行时间检查单元和一个放电 单元。 高电压产生单元产生擦除电压。 电压电平检测单元检测擦除电压并产生电平检测信号。 当擦除电压达到目标电压时，电平检测信号被激活。 执行时间检查单元生成响应于从电平检测信号的激活而经过擦除执行时间而被激活的执行结束信号。 放电单元将擦除电压作为放电电压放电。 响应于执行结束信号的激活，高电压生成单元被禁用，并且放电单元响应于执行结束信号的激活而被使能。

公开(公告)号：US07382663B2

公开(公告)日：2008-06-03

申请号：US11567895

申请日：2006-12-07

申请人： Dae-Sik Park ,  Jin-Yub Lee

发明人： Dae-Sik Park ,  Jin-Yub Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/30 ,  G11C16/16

摘要： An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.

摘要翻译： 提供均匀擦除执行时间的擦除电压产生电路和具有该擦除执行时间的非易失性半导体存储器件，其中擦除电压产生电路包括高电压产生单元，电压电平检测单元，执行时间检查单元和 放电单元 高电压产生单元产生擦除电压。 电压电平检测单元检测擦除电压并产生电平检测信号。 当擦除电压达到目标电压时，电平检测信号被激活。 执行时间检查单元生成响应于从电平检测信号的激活而经过擦除执行时间而被激活的执行结束信号。 放电单元将擦除电压作为放电电压放电。 响应于执行结束信号的激活，高电压生成单元被禁用，并且放电单元响应于执行结束信号的激活而被使能。

公开(公告)号：US08035137B2

公开(公告)日：2011-10-11

申请号：US12341812

申请日：2008-12-22

申请人： Dae-Sik Park

发明人： Dae-Sik Park

IPC分类号： G01N27/327

CPC分类号： G11C13/0009 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0033 ,  G11C2213/79 ,  H01G4/33 ,  H01G9/22 ,  H01G11/02 ,  H01G11/26 ,  H01G11/30 ,  H01G11/56 ,  H01G11/84 ,  H01L27/10852 ,  H01L28/91 ,  H01L51/0595 ,  Y02E60/13

摘要： A molecular electronic device, and a method of fabricating the same, includes a first electrode having a plurality of prominences and depressions on which a plurality of molecules are self-assembled. Capacitance of a molecular electronic device used as a capacitor is increased by forming prominences and depressions on the surface of the first electrode thereby enabling more molecules to be self-assembled on the surface of the lower electrode.

摘要翻译： 分子电子器件及其制造方法包括具有多个突起和凹陷的第一电极，多个分子在其上自组装在该第一电极上。 通过在第一电极的表面上形成凸起和凹陷来增加用作电容器的分子电子器件的电容，从而使得能够在下电极的表面上自组装更多的分子。