公开(公告)号：US20110097888A1

公开(公告)日：2011-04-28

申请号：US12929125

申请日：2011-01-03

申请人： Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

发明人： Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

IPC分类号： H01L21/28

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

摘要翻译： 半导体存储器件包括具有层叠栅结构的多个晶体管。 每个晶体管包括半导体衬底，形成在半导体衬底上的栅极绝缘体，形成在半导体衬底上的栅极绝缘体插入的下栅极，形成在下栅极上的栅极绝缘体和在下栅极上形成并硅化的上栅极 间隔绝缘体插入。 晶体管的一部分具有通过栅极间绝缘体形成的孔，以将下栅极与上栅极连接，并且还包括由绝缘体构成并形成为小于上栅极且大于上栅极上方的孔的阻挡膜以覆盖 光圈。

公开(公告)号：US07687387B2

公开(公告)日：2010-03-30

申请号：US12193349

申请日：2008-08-18

申请人： Jungo Inaba ,  Daina Inoue ,  Mutsumi Okajima

发明人： Jungo Inaba ,  Daina Inoue ,  Mutsumi Okajima

IPC分类号： H01L21/3205

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section being thinned by the etching.

摘要翻译： 根据本发明的实施例的制造半导体器件的方法包括在衬底上沉积第一至第三掩模层，处理第三掩模层，处理第二掩模层，使L / S部分中的第二掩模层变薄，以及 在L / S部分之外，将L / S部分中的第三掩模层剥离出L / S部分，在L / S部分中的第二掩模层的侧壁上形成间隔物，并在L / S部分之外 在L / S部分中的第二掩模层被抗蚀剂覆盖的条件下，在L / S部分中蚀刻第二掩模层，以除去L / S部分中的第二掩模层，而第二掩模层 保留L / S部分之外的掩模层，并且通过蚀刻处理第一掩模层，使用L / S部分中的间隔物并将L / S部分和L / S部分之外的第二掩模层作为 掩模，L / S部分中的间隔物和L / S部分和第二掩模层o之外的间隔物 通过蚀刻使L / S部分变薄。

公开(公告)号：US20120032266A1

公开(公告)日：2012-02-09

申请号：US13198081

申请日：2011-08-04

申请人： Daina INOUE ,  Minori KAJIMOTO ,  Tatsuya KATO

发明人： Daina INOUE ,  Minori KAJIMOTO ,  Tatsuya KATO

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11519 ,  H01L21/0337 ,  H01L27/11521

摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a memory cell region defined in the semiconductor substrate; and a line-and-space pattern formed in the memory cell region in which the lines constitute an active region and the spaces constitute an element isolation region. The first and the second lines of the active region counted from two opposing ends of the memory cell region are each separated into two or more line segments. The segment ends of the line segments of the first and the second lines are linked to form a loop by a linking pattern.

摘要翻译： 公开了一种半导体器件。 半导体器件包括半导体衬底; 限定在所述半导体衬底中的存储单元区域; 以及形成在存储单元区域中的线和空间图案，其中线构成有源区域，并且空间构成元件隔离区域。 从存储单元区域的两个相对端计数的有源区域的第一和第二行分别分成两个或更多个线段。 第一和第二行的线段的段末端被链接以通过链接模式形成循环。

公开(公告)号：US20090050951A1

公开(公告)日：2009-02-26

申请号：US12193349

申请日：2008-08-18

申请人： Jungo Inaba ,  Daina Inoue ,  Mutsumi Okajima

发明人： Jungo Inaba ,  Daina Inoue ,  Mutsumi Okajima

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section Is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section being thinned by the etching.

摘要翻译： 根据本发明的实施例的制造半导体器件的方法包括在衬底上沉积第一至第三掩模层，处理第三掩模层，处理第二掩模层，使L / S部分中的第二掩模层变薄，以及 在L / S部分之外，将L / S部分中的第三掩模层剥离出L / S部分，在L / S部分中的第二掩模层的侧壁上形成间隔物，并在L / S部分之外 在L / S部分中的第二掩模层被抗蚀剂覆盖的条件下，在L / S部分中蚀刻第二掩模层，以除去L / S部分中的第二掩模层，而第二掩模层 保留L / S部分之外的掩模层，并且通过蚀刻处理第一掩模层，使用L / S部分中的间隔物并将L / S部分和L / S部分之外的第二掩模层作为 掩模，L / S部分中的间隔物和L / S部分和第二掩模层o之外的间隔物 通过蚀刻使L / S部分变薄。

公开(公告)号：US08592887B2

公开(公告)日：2013-11-26

申请号：US13332905

申请日：2011-12-21

申请人： Daina Inoue ,  Hidenobu Nagashima ,  Akira Yotsumoto

发明人： Daina Inoue ,  Hidenobu Nagashima ,  Akira Yotsumoto

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L21/764

摘要： A semiconductor storage device includes an interlayer insulating film provided between select gate electrodes, a first fill material extending along upper portions of memory cell gate electrodes so as to cover air gaps residing between the memory cell gate electrodes, the first fill material extending along sidewalls of the select gate electrodes and sidewalls of the interlayer insulating film so as to define a recess above the first fill material extending along the sidewalls of the select gate electrodes and the sidewalls of the interlayer insulating film, a second fill material filling the recess above the first fill material, and a plurality of contacts formed through the interlayer insulating film, the contacts physically contacting each of device areas formed in a semiconductor substrate.

摘要翻译： 半导体存储装置包括设置在选择栅电极之间的层间绝缘膜，沿着存储单元栅电极的上部延伸的第一填充材料，以覆盖位于存储单元栅电极之间的空气间隙，第一填充材料沿着 所述选择栅极电极和所述层间绝缘膜的侧壁，以便限定沿所述选择栅电极的侧壁和所述层间绝缘膜的侧壁延伸的所述第一填充材料上方的凹部，填充所述第一填充材料上方的所述凹部的第二填充材料 填充材料和通过层间绝缘膜形成的多个触点，触点物理接触形成在半导体衬底中的每个器件区域。

公开(公告)号：US08460997B2

公开(公告)日：2013-06-11

申请号：US12929125

申请日：2011-01-03

申请人： Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

发明人： Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

IPC分类号： H01L21/302

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

摘要翻译： 半导体存储器件包括具有层叠栅结构的多个晶体管。 每个晶体管包括半导体衬底，形成在半导体衬底上的栅极绝缘体，形成在半导体衬底上的栅极绝缘体插入的下栅极，形成在下栅极上的栅极绝缘体和在下栅极上形成并硅化的上栅极 间隔绝缘体插入。 晶体管的一部分具有通过栅极间绝缘体形成的孔，以将下栅极与上栅极连接，并且还包括由绝缘体构成并形成为小于上栅极且大于上栅极上方的孔的阻挡膜以覆盖 光圈。

公开(公告)号：US20120061837A1

公开(公告)日：2012-03-15

申请号：US13230106

申请日：2011-09-12

申请人： Daina INOUE ,  Minori KAJIMOTO

发明人： Daina INOUE ,  Minori KAJIMOTO

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76834

摘要： In a method of manufacturing a semiconductor device according to an embodiment, an etching stopper, an oxide film and a mask material are formed. A trench pattern is formed in the mask material. The oxide film is etched to form the trench pattern therein by using the mask material having the trench pattern formed therein as a mask. The etching stopper is etched until the etching stopper is penetrated to form the trench pattern therein, by using the oxide film having the trench pattern formed therein as a mask. A Cu film is formed to be filled in the trench pattern formed in the etching stopper and the oxide film and to cover the top surface of the oxide film. CMP is performed on the Cu film and the oxide film until the top surface of the etching stopper serving as a stopper is exposed.

摘要翻译： 在根据实施例的半导体器件的制造方法中，形成蚀刻停止层，氧化膜和掩模材料。 在掩模材料中形成沟槽图案。 通过使用其中形成有沟槽图案的掩模材料作为掩模，蚀刻氧化膜以形成其中的沟槽图案。 通过使用其中形成有沟槽图案的氧化膜作为掩模，蚀刻蚀刻停止器直到蚀刻阻挡件被穿透以形成其中的沟槽图案。 形成Cu膜以填充在形成在蚀刻阻挡层和氧化物膜中的沟槽图案中并覆盖氧化膜的顶表面。 在Cu膜和氧化膜上进行CMP，直到作为止动件的蚀刻止挡件的顶面露出。

公开(公告)号：US20120256263A1

公开(公告)日：2012-10-11

申请号：US13332905

申请日：2011-12-21

申请人： Daina INOUE ,  Hidenobu Nagashima ,  Akira Yotsumoto

发明人： Daina INOUE ,  Hidenobu Nagashima ,  Akira Yotsumoto

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L27/11524 ,  H01L21/764

摘要： A semiconductor storage device includes an interlayer insulating film provided between select gate electrodes, a first fill material extending along upper portions of memory cell gate electrodes so as to cover air gaps residing between the memory cell gate electrodes, the first fill material extending along sidewalls of the select gate electrodes and sidewalls of the interlayer insulating film so as to define a recess above the first fill material extending along the sidewalls of the select gate electrodes and the sidewalls of the interlayer insulating film, a second fill material filling the recess above the first fill material, and a plurality of contacts formed through the interlayer insulating film, the contacts physically contacting each of device areas formed in a semiconductor substrate.

摘要翻译： 半导体存储装置包括设置在选择栅电极之间的层间绝缘膜，沿着存储单元栅电极的上部延伸的第一填充材料，以覆盖位于存储单元栅电极之间的空气间隙，第一填充材料沿着 所述选择栅极电极和所述层间绝缘膜的侧壁，以便限定沿所述选择栅电极的侧壁和所述层间绝缘膜的侧壁延伸的所述第一填充材料上方的凹部，填充所述第一填充材料上方的所述凹部的第二填充材料 填充材料和通过层间绝缘膜形成的多个触点，触点物理接触形成在半导体衬底中的每个器件区域。

公开(公告)号：US20090096007A1

公开(公告)日：2009-04-16

申请号：US12244523

申请日：2008-10-02

申请人： Mitsuhiro OMURA ,  Satoshi NAGASHIMA ,  Katsunori YAHASHI ,  Jungo INABA ,  Daina INOUE

发明人： Mitsuhiro OMURA ,  Satoshi NAGASHIMA ,  Katsunori YAHASHI ,  Jungo INABA ,  Daina INOUE

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

摘要翻译： 半导体存储器件包括具有层叠栅结构的多个晶体管。 每个晶体管包括半导体衬底，形成在半导体衬底上的栅极绝缘体，形成在半导体衬底上的栅极绝缘体插入的下栅极，形成在下栅极上的栅极绝缘体和在下栅极上形成并硅化的上栅极 间隔绝缘体插入。 晶体管的一部分具有通过栅极间绝缘体形成的孔，以将下栅极与上栅极连接，并且还包括由绝缘体构成并形成为小于上栅极且大于上栅极上方的孔的阻挡膜以覆盖 光圈。