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    Boundary scan latch configuration for generalized scan designs
    1.
    发明授权
    Boundary scan latch configuration for generalized scan designs 失效
    用于广义扫描设计的边界扫描锁存器配置

    公开(公告)号：US06195775B1

    公开(公告)日：2001-02-27

    申请号：US09145724

    申请日：1998-09-02

    申请人： Steven Michael Douskey ,  Paul Allen Ganfield ,  Daniel Guy Young

    发明人： Steven Michael Douskey ,  Paul Allen Ganfield ,  Daniel Guy Young

    IPC分类号： G01R3128

    CPC分类号： G01R31/318541

    摘要： A boundary configuration (Common Input/output CIO) for Generalized Scan Designs (GSD) in a single clock chip design includes at least one generalized scan design internal latch; a boundary scan clock input to the internal latch; an input/output cell connected to the internal latch; and at least one control line between the internal latch and the input/output cell. The CIO GSD is arranged and configured to operate in various modes including a function mode, a RUNBIST/INTEST/LBIST mode, an EXTEST/WIRETEST mode, a SAMPLE/PRELOAD mode, etc. In a different version, a MUX controller is connected to the internal latch. The MUX controller selects data from one of at least two control lines and sending the selected data to at least one internal logic unit of the chip for a test operation.

    摘要翻译： 在单时钟芯片设计中的通用扫描设计（GSD）的边界配置（公共输入/输出CIO）包括至少一个通用扫描设计内部锁存器; 边界扫描时钟输入到内部锁存器; 连接到内部锁存器的输入/输出单元; 以及内部锁存器和输入/输出单元之间的至少一个控制线。 CIO GSD被布置和配置为以各种模式操作，包括功能模式，RUNBIST / INTEST / LBIST模式，EXTEST / WIRETEST模式，SAMPLE / PRELOAD模式等。在不同的版本中，MUX控制器连接到 内部闩锁。 MUX控制器从至少两条控制线之一中选择数据，并将所选择的数据发送到用于测试操作的芯片的至少一个内部逻辑单元。

    System and method for minimizing simultaneous switching during scan-based testing
    2.
    发明授权
    System and method for minimizing simultaneous switching during scan-based testing 失效
    用于在基于扫描的测试期间最小化同时切换的系统和方法

    公开(公告)号：US5663966A

    公开(公告)日：1997-09-02

    申请号：US686105

    申请日：1996-07-24

    申请人： Leland Leslie Day ,  Steven Michael Douskey ,  Paul Allen Ganfield

    发明人： Leland Leslie Day ,  Steven Michael Douskey ,  Paul Allen Ganfield

    IPC分类号： G01R31/3185 ,  H04B17/00

    CPC分类号： G01R31/318541

    摘要： A system and method for reducing simultaneous switching during scan-based testing of a system logic design. System logic is divided into clusters of system logic, and one or more scan chains are associated with each logic cluster. Each of the logic clusters are concurrently scan tested, yet circuitry in the scan chains associated with a cluster are triggered at different times than the circuitry in the scan chains of other clusters. Offset scan control signals provide the triggering for the scan chains of different clusters. Release and capture functions are also controlled to reduce simultaneous release and capture switching in different clusters.

    摘要翻译： 一种在系统逻辑设计的基于扫描的测试期间减少同时切换的系统和方法。 系统逻辑被分为系统逻辑的集群，并且一个或多个扫描链与每个逻辑集群相关联。 每个逻辑集群被同时扫描测试，但与集群相关联的扫描链中的电路在与其他集群的扫描链中的电路不同的时间被触发。 偏移扫描控制信号为不同簇的扫描链提供触发。 释放和捕获功能也受到控制，以减少不同群集中同时的释放和捕获切换。

    Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof
    3.
    发明授权
    Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof 失效
    数据处理系统，电路布置和程序产品，包括多路径扫描接口及其方法

    公开(公告)号：US6158032A

    公开(公告)日：2000-12-05

    申请号：US49170

    申请日：1998-03-27

    申请人： Guy Richard Currier ,  Leland Leslie Day ,  Steven Michael Douskey ,  Paul Allen Ganfield ,  James Maurice Wallin

    发明人： Guy Richard Currier ,  Leland Leslie Day ,  Steven Michael Douskey ,  Paul Allen Ganfield ,  James Maurice Wallin

    IPC分类号： G01R31/3185 ,  G01R31/28

    CPC分类号： G01R31/318536

    摘要： A data processing system, circuit arrangement, program product, and method thereof utilize a multi-path scan interface that is capable of providing multiple scan paths into a plurality of scan ring segments in an integrated circuit device. The multi-path scan interface utilizes one or more multiplexers coupled between scan in and scan out ports and at least one scan ring segment to provide alternate scan paths depending upon select signals supplied to each multiplexer. With such a configuration, a standardized scan interface may developed for interfacing with a wide variety of scan ring segments, and optionally, for multiple purposes. As a result, the amount of custom circuitry necessary to provide access to scan ring segments is significantly reduced.

    摘要翻译： 数据处理系统，电路装置，程序产品及其方法利用能够向集成电路装置中的多个扫描环段提供多条扫描路径的多路径扫描接口。 多路径扫描接口利用耦合在扫描入口和扫描端口中的一个或多个多路复用器和至少一个扫描环段，以根据提供给每个多路复用器的选择信号提供交替的扫描路径。 利用这种配置，可以开发用于与各种各样的扫描环段对接的标准化扫描界面，并且可选地，出于多个目的。 因此，提供访问扫描环段所需的定制电路的量显着减少。

    Method and apparatus for managing write-to-read turnarounds in an early read after write memory system
    4.
    发明授权
    Method and apparatus for managing write-to-read turnarounds in an early read after write memory system 有权
    用于在写入存储器系统之后的早期读取中管理写入读取周转的方法和装置

    公开(公告)号：US07321950B2

    公开(公告)日：2008-01-22

    申请号：US11050021

    申请日：2005-02-03

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    IPC分类号： G06F12/00

    CPC分类号： G06F13/161 ,  G06F13/1647

    摘要： A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

    摘要翻译： 提出了一种用于在写入存储器系统之后的早期读取中管理写入到读取周转的方法和装置。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

    Managing write-to-read turnarounds in an early read after write memory system
    5.
    发明授权
    Managing write-to-read turnarounds in an early read after write memory system 有权
    在写入内存系统之后的早期读取中管理写入阅读的周转时间

    公开(公告)号：US07487318B2

    公开(公告)日：2009-02-03

    申请号：US11851468

    申请日：2007-09-07

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F13/161 ,  G06F13/1647

    摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

    摘要翻译： 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

    Memory controller operating in a system with a variable system clock
    6.
    发明授权
    Memory controller operating in a system with a variable system clock 有权
    内存控制器在具有可变系统时钟的系统中运行

    公开(公告)号：US07467277B2

    公开(公告)日：2008-12-16

    申请号：US11348879

    申请日：2006-02-07

    申请人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

    发明人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

    IPC分类号： G06F13/14

    CPC分类号： G11C8/18 ,  G06F13/1642 ,  G06F13/1689 ,  Y02D10/14

    摘要： The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

    摘要翻译： 本发明一般涉及在包含可变系统时钟的系统中操作的存储器控​​制器。 存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。 然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。 可以提供异步缓冲器以跨可变和恒定时钟域传输数据。 为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。 为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

    Methods and Apparatus for Interfacing a Processor and a Memory
    7.
    发明申请
    Methods and Apparatus for Interfacing a Processor and a Memory 审中-公开
    用于接口处理器和存储器的方法和装置

    公开(公告)号：US20080168206A1

    公开(公告)日：2008-07-10

    申请号：US11620110

    申请日：2007-01-05

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    IPC分类号： G06F13/14

    CPC分类号： G06F13/4059

    摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a first memory; (b) a processor adapted to issue a functional command to the first memory; (c) a translation chip; (d) a cache memory coupled to the translation chip; (e) a first link adapted to couple the processor to the translation chip; and (f) a second link adapted to couple the translation chip to the first memory; and (2) calibrating the first link to transmit data between the processor and cache memory. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）第一存储器的计算机系统; （b）适于向第一存储器发出功能命令的处理器; （c）翻译芯片; （d）耦合到所述平移芯片的高速缓冲存储器; （e）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（f）适于将所述翻译芯片耦合到所述第一存储器的第二链路; 和（2）校准第一链路以在处理器和高速缓冲存储器之间传送数据。 提供了许多其他方面。

    Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate Memory
    9.
    发明申请
    Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate Memory 审中-公开
    使用极限数据速率存储器命令来刷新和刷新双倍数据速率存储器

    公开(公告)号：US20080183916A1

    公开(公告)日：2008-07-31

    申请号：US11668531

    申请日：2007-01-30

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Ryan Abel Heckendorf ,  John David Irish ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Ryan Abel Heckendorf ,  John David Irish ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    IPC分类号： G06F13/00

    CPC分类号： G06F11/106

    摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供适于发出符合第一协议的命令的处理器; （2）提供耦合到所述处理器的存储器，并且可通过符合第二协议的命令来访问; （3）采用符合第二协议的多个擦除命令来检查存储器的相应部分的错误，其中符合第二协议的每个擦除命令是符合由处理器发出的第一协议的擦除命令的转换版本 并且各部分是非顺序的; 和（4）在预定时间段内刷新存储在整个存储器中的位。 提供了许多其他方面。

    Methods and Apparatus for Calibrating Heterogeneous Memory Interfaces
    10.
    发明申请
    Methods and Apparatus for Calibrating Heterogeneous Memory Interfaces 审中-公开
    用于校准异构存储器接口的方法和装置

    公开(公告)号：US20080168298A1

    公开(公告)日：2008-07-10

    申请号：US11620104

    申请日：2007-01-05

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    IPC分类号： G06F12/00 ,  G06F1/08

    CPC分类号： G11C7/10 ,  G11C2207/2254

    摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a memory; (b) a processor adapted to issue a functional command to the memory; (c) a translation chip; (d) a first link adapted to couple the processor to the translation chip; and (e) a second link adapted to couple the translation chip to the memory; (2) calibrating the first link using the translation chip; and (3) while calibrating the first link, calibrating the second link using the translation chip. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）存储器的计算机系统; （b）适于向存储器发出功能命令的处理器; （c）翻译芯片; （d）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（e）适于将所述翻译芯片耦合到所述存储器的第二链接; （2）使用翻译芯片校准第一链接; 和（3）在校准第一链路的同时，使用转换芯片校准第二链路。 提供了许多其他方面。