公开(公告)号：US5081574A

公开(公告)日：1992-01-14

申请号：US566871

申请日：1990-02-26

申请人： Larry D. Larsen ,  Daniel J. Esteban

发明人： Larry D. Larsen ,  Daniel J. Esteban

IPC分类号： G06F9/38 ,  G06F17/10

CPC分类号： G06F17/10 ,  G06F9/3842

摘要： The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of "hot bits" existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the same time that the branch will be executed. The conditions which may be used to trigger a branching decision may also result from the ALU operation output or from the state of a selected data bus bit. The instructions providing the branch conditions must not be separated from the associated branch instruction. Therefore, to prevent separation of these two instructions, interrupt protection is always provided for such sequences. Indirect branching is also accommodated by making available the contents of a common data bus to be placed in the instruction address register that would be branched to. The contents of the data bus depend upon the instruction which executes simultaneously with the branch instruction, i.e., that which is in the third phase in the pipeline. Interrupt protection is therefore required for these types of branching actions as well.

摘要翻译： 在本发明中使用的处理器的架构和指令允许有效地完成信号处理任务。 用于指令的三相流水线操作包括获取，解码和执行操作。 为了提供额外的灵活性并减少分支延迟，除了分支指令之外执行的所有指令都在第三阶段执行。 分支指令在第二阶段结束时执行。 分支条件可以基于在第二周期期间在处理器内存在的“热位”，并且是由于执行在分支指令之前的指令而导致的。 条件分支是根据执行此类指令而导致的先前未被锁存到寄存器中的条件执行的。 这些条件是在分支执行的同时生成的。 可用于触发分支决定的条件也可能由ALU操作输出或从所选数据总线位的状态产生。 提供分支条件的指令不能与关联的分支指令分离。 因此，为了防止这两个指令的分离，始终为这些序列提供中断保护。 间接分支也可以通过提供将被分配到指令地址寄存器中的公共数据总线的内容来实现。 数据总线的内容取决于与分支指令同时执行的指令，即在流水线中处于第三阶段的指令。 因此，这些类型的分支动作也需要中断保护。

公开(公告)号：US4464783A

公开(公告)日：1984-08-07

申请号：US369997

申请日：1982-04-20

申请人： Jean-Paul Beraud ,  Daniel J. Esteban ,  Claude Galand

发明人： Jean-Paul Beraud ,  Daniel J. Esteban ,  Claude Galand

IPC分类号： H03M3/02 ,  H03M7/30 ,  H04B1/66 ,  H04B14/04 ,  G10L1/00

CPC分类号： H04B1/667

摘要： This improved speech signal Block Coded PCM (BCPCM) system reduces the number of bits allocated to transmitting the scale factor, thereby releasing bits for allocation to coding samples in the associated block of samples. The scale factor (c) is calculated for every 16 millisecond block of samples. However, the scale factor will be transmitted only once per 32 millisecond block if there is no significant difference between the two sequential values. The original speech signal is split into 16 frequency subbands, each subband initials sampled and 12-bit coded, then requantized in BCPCM at dynamically variable bit rates depending on the scale factor transmission rate.

摘要翻译： 这种改进的语音信号块编码PCM（BCPCM）系统减少了分配给发送比例因子的比特数，从而释放用于分配给相关采样块中的编码样本的比特。 每16毫秒样本块计算比例因子（c）。 但是，如果两个顺序值之间没有显着差异，则缩放因子将仅在每32毫秒块传输一次。 原始语音信号分为16个频率子带，每个子带采样和12位编码，然后根据比例因子传输速率以动态可变比特率在BCPCM中重新量化。

公开(公告)号：US4216354A

公开(公告)日：1980-08-05

申请号：US964324

申请日：1978-11-29

申请人： Daniel J. Esteban ,  Claude R. Galand ,  Daniel Mauduit ,  Jean Menez

发明人： Daniel J. Esteban ,  Claude R. Galand ,  Daniel Mauduit ,  Jean Menez

IPC分类号： H03M7/30 ,  H04B1/66 ,  H04B14/04 ,  G10L1/00

CPC分类号： H04B1/667

摘要： A voice signal is transmitted digitally at reduced bit rate by use of data compression. The original frequency components of a telephone band width of the voice signal sampled at 8 KHz and quantized with 12 bits are transformed into three parameters: SIGNAL data representing adaptive quantization for lower frequency (300-800 Hz) sub-bands; COEF data representing pre-emphasized parcor type coefficients for the higher frequency (800-3000 Hz) band; and, ENERGY data representing higher frequency short term energy level. The three parameters are multiplexed for transmission in binary-code form, thereby representing a recoding of the original binary-coded voice signals.

摘要翻译： 语音信号通过使用数据压缩以降低的比特率数字地发送。 以8KHz采样并用12位量化的语音信号的电话频带宽度的原始频率分量被转换为三个参数：表示低频（300-800Hz）子频带的自适应量化的信号数据; COEF数据代表较高频率（800-3000Hz）频带的预先强调的parcor类型系数; 以及表示较高频率的短期能级的ENERGY数据。 三个参数被多路复用以二进制码形式传输，从而表示原始二进制编码语音信号的重新编码。

公开(公告)号：US4051470A

公开(公告)日：1977-09-27

申请号：US672203

申请日：1976-03-31

申请人： Daniel J. Esteban ,  Jean E. Menez

发明人： Daniel J. Esteban ,  Jean E. Menez

IPC分类号： H03M1/12 ,  H03M1/00 ,  H03M3/02 ,  H03M3/04 ,  H03M7/30 ,  H03K13/22

CPC分类号： H03M7/3053 ,  H03M3/022

摘要： This is a block quantizer which converts a given block of samples into an optimum sequence of numbers describing the sampled signal with minimum distortion due to the quantizing process.The quantizer self-adjusts the basic parameters, i.e., quantizing step Q, d.c. level C and the sequence of numbers fn, describing the signal for each block of samples for a minimal Mean Squared Error.

公开(公告)号：US4455649A

公开(公告)日：1984-06-19

申请号：US339592

申请日：1982-01-15

申请人： Daniel J. Esteban ,  Gardner D. Jones, Jr. ,  Lee S. Rogers

发明人： Daniel J. Esteban ,  Gardner D. Jones, Jr. ,  Lee S. Rogers

IPC分类号： H04M11/06 ,  H03M7/30 ,  H04B1/66 ,  H04B14/04 ,  H04J1/00 ,  H04J3/00 ,  H04J3/04 ,  H04J3/16 ,  H04J3/17 ,  H04J4/00 ,  H04J6/02

CPC分类号： H04J3/1688 ,  H04B1/667

摘要： The improved multiplexer described herein uses split band encoding across a plurality of input ports to increase the statistical advantage for compression gains but does not require a large number of input ports to achieve its advantage.

摘要翻译： 这里描述的改进的多路复用器使用跨多个输入端口的分段编码来增加压缩增益的统计优点，但是不需要大量的输入端口来实现其优点。

公开(公告)号：US4794517A

公开(公告)日：1988-12-27

申请号：US723991

申请日：1985-04-15

申请人： Gardner D. Jones ,  Larry D. Larsen ,  Daniel J. Esteban

发明人： Gardner D. Jones ,  Larry D. Larsen ,  Daniel J. Esteban

IPC分类号： G06F9/48 ,  G06F9/38 ,  G06F17/10 ,  G06F15/00

CPC分类号： G06F9/3889 ,  G06F17/10 ,  G06F9/3861

摘要： This processor is a single chip implementation of an architecture that is designed to expeditiously handle certain tasks commonly associated with signal processing. Sequential multiply and accumulate operations, in particular, can be accomplished quite efficiently. The processor is pipelined in two areas. Instructions are passed through a three phase pipeline and consist of fetch, decode and execute, while the multiplier utilizes a two phase pipeline. The data flow is parallel and of 16-bit width throughout. The instruction store is maintained separately from the data store and provisions are included for having the processor enabled to read and write its own instruction store. Some parallel or compound instructions are implemented to permit transfer actions such as storage or I/O to or from instruction registers to occur concurrently with a compute action in different segments of the data flow. The arithmetic capabilities of the processor include both the separate multiplier and a full arithmetic logic unit. Two DMA modes are permitted. Extensive diagnostic capabilities, some of which utilize the processor's ability to read and write its own instruction store, are also included.

摘要翻译： 该处理器是一种架构的单芯片实现，旨在快速处理通常与信号处理相关的某些任务。 特别是顺序乘法和积累操作可以非常有效地完成。 处理器在两个区域流水线化。 指令通过三相流水线，包括获取，解码和执行，而乘法器使用两相管道。 数据流是并行的，整个16位宽。 指令存储器与数据存储器分开维护，并且包括用于使处理器能够读取和写入其自己的指令存储器的规定。 实现一些并行或复合指令以允许向指令寄存器发送存储或I / O的传送动作与数据流的不同段中的计算动作同时发生。 处理器的算术能力包括单独的乘法器和完整的算术逻辑单元。 允许两种DMA模式。 广泛的诊断功能，其中一些利用处理器读写自己的指令存储库的能力也包括在内。