-
公开(公告)号：US07075822B2
公开(公告)日：2006-07-11
申请号：US10335961
申请日：2002-12-31
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C11/56 , G11C16/04 , G11C16/10 , G11C29/16 , G11C29/36 , G11C29/38 , G11C29/50004 , G11C29/52 , G11C2029/5002 , G11C2211/5641
摘要： An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.
-
公开(公告)号：US06747893B2
公开(公告)日：2004-06-08
申请号：US10099678
申请日：2002-03-14
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C16/12 , G11C2216/16
摘要： Cells in a non-volatile memory are programmed in parallel using a variable program bandwidth. The variable program bandwidth is an automatic variation in the number of cells pulsed in parallel based upon a predefined electrical current provisioning capability. The variation in programming number may be based upon whether a program pulse represents an initial pulse or a re-pulse. Additionally, or alternatively, the variation in programming number may be based upon a cell level to be programmed by a pulse in a MLC device.
摘要翻译： 使用可变程序带宽并行编程非易失性存储器中的单元。 可变程序带宽是基于预定义的电流供应能力而并行脉冲的单元的数量的自动变化。 节目编号的变化可以基于节目脉冲是表示初始脉冲还是重新脉冲。 另外或替代地，编程编号的变化可以基于要由MLC设备中的脉冲编程的单元级。
-
公开(公告)号：US06809962B2
公开(公告)日：2004-10-26
申请号：US10738739
申请日：2003-12-16
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C16/12 , G11C2216/16
摘要： Cells in a non-volatile memory are programmed in parallel using a variable program bandwidth. The variable program bandwidth is an automatic variation in the number of cells pulsed in parallel based upon a predefined electrical current provisioning capability. The variation in programming number may be based upon whether a program pulse represents an initial pulse or a re-pulse. Additionally, or alternatively, the variation in programming number may be based upon a cell level to be programmed by a pulse in a MLC device.
摘要翻译： 使用可变程序带宽并行编程非易失性存储器中的单元。 可变程序带宽是基于预定义的电流供应能力而并行脉冲的单元的数量的自动变化。 节目编号的变化可以基于节目脉冲是表示初始脉冲还是重新脉冲。 另外或替代地，编程编号的变化可以基于要由MLC设备中的脉冲编程的单元级。
-
公开(公告)号：US06700820B2
公开(公告)日：2004-03-02
申请号：US10038119
申请日：2002-01-03
IPC分类号： G11C1606
CPC分类号： G11C11/5628 , G11C16/3454
摘要： Programming non-volatile memory devices includes identifying addresses in a data buffer for storing a particular one of a plurality of threshold voltage levels, then pulsing the array memory cells to program the array memory cells to the particular threshold voltage level. The identifying and pulsing is repeated for each of the threshold voltage levels.
摘要翻译： 编程非易失性存储器件包括识别用于存储多个阈值电压电平中的特定一个的数据缓冲器中的地址，然后脉冲阵列存储器单元将阵列存储器单元编程到特定阈值电压电平。 针对每个阈值电压电平重复识别和脉冲。
-
5.发明授权Global/local memory decode with independent program and read paths and shared local decode 失效全局/本地存储器解码，具有独立的程序和读取路径以及共享本地解码公开(公告)号：US06480417B2
公开(公告)日：2002-11-12
申请号：US09809416
申请日：2001-03-15
申请人： Daniel R. Elmhurst
发明人： Daniel R. Elmhurst
IPC分类号： G11C1604
CPC分类号： G11C16/24 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A memory cell selection scheme that permits simultaneous reading and writing of cells in different memory blocks by using separate routing for bias voltages to the cells. A read path and a program path are used to separately route the read and program voltages to a memory block. Separate read and program transistors are used to selectively route one of those two voltages to a regional voltage line, where individual local voltage transistors can selectively route voltage from the regional voltage line to local voltage lines. By placing a separate set of read and program transistors in each block, each block can be configured to conduct either read or program operations without regard to which of those functions is being performed in other blocks.
摘要翻译： 一种存储器单元选择方案，其允许通过使用用于单元的偏置电压的单独路由来同时读取和写入不同存储器块中的单元。 读取路径和程序路径用于将读取和编程电压分别路由到存储块。 单独的读取和编程晶体管用于选择性地将这两个电压之一路由到区域电压线路，其中各个本地电压晶体管可以选择性地将电压从区域电压线路路由到局部电压线路。 通过在每个块中放置单独的一组读取和编程晶体管，每个块可以配置为进行读取或编程操作，而不考虑在其他块中执行哪些功能。
-
公开(公告)号：US06356062B1
公开(公告)日：2002-03-12
申请号：US09670850
申请日：2000-09-27
IPC分类号： G05F156
CPC分类号： H02M3/073 , Y10S323/907
摘要： A regulator circuit to control the output of a charge pump circuit, to reduce the effects of operating temperature and process variations on available output current from the charge pump circuit. A predetermined fraction of the output voltage of the charge pump circuit is fed back to the input of a differential amplifier, which compares it to a reference voltage. The output of the differential amplifier feeds a voltage controlled oscillator (VCO), which in turn generates a clock signal that is used to drive the charge pump circuit. The normal temperature characteristics of this configuration cause the output of the charge pump circuit to degrade with temperature changes. The regulator circuit can be placed between the differential amplifier and the VCO to adjust the voltage driving the VCO. In one embodiment, a biasing resistor with a negative temperature coefficient can be used in the regulator circuit to offset the normal effects of temperature on the circuit. In another embodiment, multiple such resistors can be selectable with programmable logic, so that process variations during manufacture can be compensated for by selecting the resistor value that most closely provides optimal biasing.
摘要翻译： 用于控制电荷泵电路的输出的调节器电路，以减少来自电荷泵电路的可用输出电流的工作温度和工艺变化的影响。 电荷泵电路的输出电压的预定分数被反馈到差分放大器的输入，差分放大器将其与参考电压进行比较。 差分放大器的输出馈送压控振荡器（VCO），其又产生用于驱动电荷泵电路的时钟信号。 该配置的常温特性使电荷泵电路的输出随温度变化而降低。 调节器电路可以放置在差分放大器和VCO之间，以调节驱动VCO的电压。 在一个实施例中，可以在调节器电路中使用具有负温度系数的偏置电阻器来抵消温度对电路的正常影响。 在另一个实施例中，可以用可编程逻辑选择多个这样的电阻器，从而可以通过选择最接近地提供最佳偏置的电阻器值来补偿制造期间的工艺变化。
-
公开(公告)号：US07327605B2
公开(公告)日：2008-02-05
申请号：US11646687
申请日：2006-12-28
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C11/56 , G11C16/04 , G11C16/10 , G11C29/16 , G11C29/36 , G11C29/38 , G11C29/50004 , G11C29/52 , G11C2029/5002 , G11C2211/5641
摘要： An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.
摘要翻译： 一种用于使用高带宽数据路径架构在存储器存储设备中测试多级单元（MLC）的装置和技术。 该技术包括用于从多级单元存储器获得第一数据和第二数据的硬件。 第一数据与第二数据不同。 比较第一数据和第二数据，并且至少部分地基于该比较，对多电平单元存储器进行编程。 编程多电平单元存储器包括访问多电平单元存储器中的存储单元，并确定需要编程的第一数据的每个存储单元的位数。
-
公开(公告)号：US07177186B2
公开(公告)日：2007-02-13
申请号：US11391509
申请日：2006-03-28
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C11/56 , G11C16/04 , G11C16/10 , G11C29/16 , G11C29/36 , G11C29/38 , G11C29/50004 , G11C29/52 , G11C2029/5002 , G11C2211/5641
摘要： An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.
摘要翻译： 一种用于使用高带宽数据路径架构在存储器存储设备中测试多级单元（MLC）的装置和技术。 该技术包括用于从多级单元存储器获得第一数据和第二数据的硬件。 第一数据与第二数据不同。 比较第一数据和第二数据，并且至少部分地基于该比较，对多电平单元存储器进行编程。 编程多电平单元存储器包括访问多电平单元存储器中的存储单元，并确定需要编程的第一数据的每个存储单元的位数。
-
9.发明授权公开(公告)号：US06618287B2
公开(公告)日：2003-09-09
申请号：US10232545
申请日：2002-08-29
申请人： Daniel R. Elmhurst
发明人： Daniel R. Elmhurst
IPC分类号： G11C1604
CPC分类号： G11C16/24 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A memory cell selection scheme that permits simultaneous reading and writing of cells in different memory blocks by using separate routing for bias voltages to the cells. A read path and a program path are used to separately route the read and program voltages to a memory block. Separate read and program transistors are used to selectively route one of those two voltages to a regional voltage line, where individual local voltage transistors can selectively route voltage from the regional voltage line to local voltage lines. By placing a separate set of read and program transistors in each block, each block can be configured to conduct either read or program operations without regard to which of those functions is being performed in other blocks.
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.013 秒)
