公开(公告)号：US09575911B2

公开(公告)日：2017-02-21

申请号：US14246832

申请日：2014-04-07

Applicant: David McMenamin ,  James Andrew Collier Scobie

Inventor： David McMenamin ,  James Andrew Collier Scobie

IPC: G06F11/00 ,  G06F13/26 ,  G06F11/20

CPC classification number: G06F13/26 ,  G06F11/2069 ,  G06F11/2089 ,  G06F11/2092 ,  G06F11/2094 ,  G06F2201/805

Abstract: An interrupt controller for controlling processing of interrupt requests by a plurality of processing units. The processing units have at least two modes: an active mode and an inactive mode. The interrupt controller comprises a controller input, an interrupt router coupled to the controller input and a monitoring unit. The monitoring unit outputs a routing change signal to the interrupt router if it determines that a selected processing unit, to which, in response to a received interrupt request, an execution of an interrupt service routine was initially routed, is in inactive mode while a preselected one is in the active mode. The interrupt router reroutes the execution of the interrupt service routine to the preselected processing unit.

Abstract translation: 一种用于控制多个处理单元对中断请求的处理的中断控制器。 处理单元至少有两种模式：活动模式和非活动模式。 中断控制器包括控制器输入，耦合到控制器输入的中断路由器和监视单元。 监控单元如果确定选择的处理单元，其响应于接收到的中断请求，中断服务程序的执行被初始路由，则向中断路由器输出路由改变信号处于非活动模式，而预选的 一个处于活动模式。 中断路由器将中断服务程序的执行重新路由到预选的处理单元。

公开(公告)号：US20150309730A1

公开(公告)日：2015-10-29

申请号：US14261589

申请日：2014-04-25

Applicant: MARK MAIOLANI ,  GORDON JAMES CAMPBELL ,  CARL CULSHAW ,  ALISTAIR JAMES GORMAN ,  DAVID MCMENAMIN

Inventor： MARK MAIOLANI ,  GORDON JAMES CAMPBELL ,  CARL CULSHAW ,  ALISTAIR JAMES GORMAN ,  DAVID MCMENAMIN

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/00 ,  G06F11/34 ,  G06F11/3648 ,  G06F13/00 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system performance control component, and method therefor, for configuring at least one system performance parameter within a signal processing system. The system performance control component is arranged to receive an indication of an address of a memory access performed by at least one signal processing component, compare the received indication of an address of a memory access to at least one address value, and configure at least one system performance parameter based at least partly on the comparison of the received indication of an address of a memory access to at least one address value.

Abstract translation: 一种系统性能控制部件及其方法，用于在信号处理系统内配置至少一个系统性能参数。 系统性能控制部件被布置为接收由至少一个信号处理部件执行的存储器访问的地址的指示，将接收到的存储器访问的指示与至少一个地址值进行比较，并配置至少一个 系统性能参数至少部分地基于存储器访问的地址的接收指示与至少一个地址值的比较。

公开(公告)号：US20150286595A1

公开(公告)日：2015-10-08

申请号：US14246832

申请日：2014-04-07

Applicant: DAVID MCMENAMIN ,  JAMES ANDREW COLLIER SCOBIE

Inventor： DAVID MCMENAMIN ,  JAMES ANDREW COLLIER SCOBIE

IPC: G06F13/26

CPC classification number: G06F13/26 ,  G06F11/2069 ,  G06F11/2089 ,  G06F11/2092 ,  G06F11/2094 ,  G06F2201/805

Abstract: An interrupt controller for controlling processing of interrupt requests by a plurality of processing units. The processing units have at least two modes: an active mode and an inactive mode. The interrupt controller comprises a controller input, an interrupt router coupled to the controller input and a monitoring unit. The monitoring unit outputs a routing change signal to the interrupt router if it determines that a selected processing unit, to which, in response to a received interrupt request, an execution of an interrupt service routine was initially routed, is in inactive mode while a preselected one is in the active mode. The interrupt router reroutes the execution of the interrupt service routine to the preselected processing unit.

Abstract translation: 一种用于控制多个处理单元对中断请求的处理的中断控制器。 处理单元至少有两种模式：活动模式和非活动模式。 中断控制器包括控制器输入，耦合到控制器输入的中断路由器和监视单元。 监控单元如果确定选择的处理单元，其响应于接收到的中断请求，中断服务程序的执行被初始路由，则将其转换到中断路由器，该选择处理单元处于非活动模式，而预选 一个处于活动模式。 中断路由器将中断服务程序的执行重新路由到预选的处理单元。

公开(公告)号：US09952922B2

公开(公告)日：2018-04-24

申请号：US14899595

申请日：2013-07-18

Applicant: Graham Edmiston ,  Alan Devine ,  David McMenamin ,  Andrew Roberston ,  James Andrew Collier Scobie

Inventor： Graham Edmiston ,  Alan Devine ,  David McMenamin ,  Andrew Roberston ,  James Andrew Collier Scobie

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/28

CPC classification number: G06F11/079 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/28

Abstract: Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

公开(公告)号：US20160239362A1

公开(公告)日：2016-08-18

申请号：US14899595

申请日：2013-07-18

Applicant: Graham EDMISTON ,  Alan DEVINE ,  David MCMENAMIN ,  Andrew ROBERTSON ,  James Andrew Collier SCOBIE

Inventor： GRAHAM EDMISTON ,  ALAN DEVINE ,  DAVID MCMENAMIN ,  ANDREW ROBERSTON ,  JAMES ANDREW COLLIER SCOBIE

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/28

Abstract: Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

Abstract translation: 适用于检测处理器中的故障的装置包括监视器，其接收来自处理器的输入和输出信号，并产生用于访问散列表中的条目的散列索引关键字。 条目可以包括诸如设置定时器的动作，使得输出对输入状态的改变的响应可以在指定的时间间隔内被确认为有效。

公开(公告)号：US09417795B2

公开(公告)日：2016-08-16

申请号：US14261589

申请日：2014-04-25

Applicant: Mark Maiolani ,  Gordon James Campbell ,  Carl Culchaw ,  Alistair James Gorman ,  David McMenamin

Inventor： Mark Maiolani ,  Gordon James Campbell ,  Carl Culchaw ,  Alistair James Gorman ,  David McMenamin

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/00 ,  G06F11/34 ,  G06F11/3648 ,  G06F13/00 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system performance control component, and method therefor, for configuring at least one system performance parameter within a signal processing system. The system performance control component is arranged to receive an indication of an address of a memory access performed by at least one signal processing component, compare the received indication of an address of a memory access to at least one address value, and configure at least one system performance parameter based at least partly on the comparison of the received indication of an address of a memory access to at least one address value.

Abstract translation: 一种系统性能控制部件及其方法，用于在信号处理系统内配置至少一个系统性能参数。 系统性能控制部件被布置为接收由至少一个信号处理部件执行的存储器访问的地址的指示，将接收到的存储器访问的指示与至少一个地址值进行比较，并配置至少一个 系统性能参数至少部分地基于存储器访问的地址的接收指示与至少一个地址值的比较。