公开(公告)号：US09395797B2

公开(公告)日：2016-07-19

申请号：US14321838

申请日：2014-07-02

Applicant: Garima Sharda ,  Carl Culshaw ,  Alan Devine ,  Akshay K. Pathak ,  Alistair P. Robertson

Inventor： Garima Sharda ,  Carl Culshaw ,  Alan Devine ,  Akshay K. Pathak ,  Alistair P. Robertson

IPC: G06F1/26 ,  G06F1/32 ,  G06F13/40

CPC classification number: G06F1/3243 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3293 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.

Abstract translation: 在高功率模式和低功率单元（LPU）运行模式下可操作的微控制器包括主和LPU域，主和LPU模式控制器以及主和LPU时钟发生器模块。 主域包括第一组电路和第一组核心。 LPU域包括第二组和第三组电路，第二组磁芯和开关模块。 在高功率模式下，交换模块将第一和第二组核心连接到第一组，第二组和第三组电路中的至少一个，而在LPU运行模式下，交换模块将LPU域与主域隔离开 并激活包括LPU域，LPU模式控制器和LPU时钟发生器模块的小型微控制器系统（SMS）。 在LPU运行模式下，SMS还具有进一步的低功耗模式。

公开(公告)号：US20110145625A1

公开(公告)日：2011-06-16

申请号：US13059246

申请日：2008-08-26

Applicant: Derek Beattie ,  Carl Culshaw ,  Alan Devine ,  James Andrew Collier Scobie

Inventor： Derek Beattie ,  Carl Culshaw ,  Alan Devine ,  James Andrew Collier Scobie

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.

Abstract translation: 时钟系统包括多个时钟数据处理装置和时钟控制电路，时钟控制电路控制多个时钟信号的产生以及时钟信号到多个数据处理装置的应用，允许对数据中的至少一个进行时钟 处理设备，同时冻结所有数据处理设备中的至少一个。 一种用于计时多个时钟数据处理装置的方法包括：控制多个时钟信号的产生并控制对多个数据处理装置的时钟信号的应用，允许在冻结期间对数据处理装置中的至少一个进行计时 所有这些数据处理设备中的至少一个。

公开(公告)号：US20160239362A1

公开(公告)日：2016-08-18

申请号：US14899595

申请日：2013-07-18

Applicant: Graham EDMISTON ,  Alan DEVINE ,  David MCMENAMIN ,  Andrew ROBERTSON ,  James Andrew Collier SCOBIE

Inventor： GRAHAM EDMISTON ,  ALAN DEVINE ,  DAVID MCMENAMIN ,  ANDREW ROBERSTON ,  JAMES ANDREW COLLIER SCOBIE

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/28

Abstract: Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

Abstract translation: 适用于检测处理器中的故障的装置包括监视器，其接收来自处理器的输入和输出信号，并产生用于访问散列表中的条目的散列索引关键字。 条目可以包括诸如设置定时器的动作，使得输出对输入状态的改变的响应可以在指定的时间间隔内被确认为有效。

公开(公告)号：US20130229737A1

公开(公告)日：2013-09-05

申请号：US13880193

申请日：2010-11-22

Applicant: Alistair Robertson ,  Carl Culshaw ,  Alan Devine

Inventor： Alistair Robertson ,  Carl Culshaw ,  Alan Devine

IPC: H02H3/20 ,  G01R19/00 ,  H03M1/12

CPC classification number: H02H3/20 ,  G01R19/0084 ,  G01R19/165 ,  H03M1/12 ,  H03M1/129

Abstract: An integrated circuit device comprising at least one analogue to digital converter. The at least one ADC comprises at least one input operably coupled to at least one external contact of the integrated circuit device. The integrated circuit device further comprises detection circuitry comprising at least one detection module. The at least one detection module being arranged to receive at a first input thereof an indication of a voltage level at the at least one input of the at least one ADC, compare the received indication to a threshold value, and if the received indication exceeds the threshold value, output an indication that an excessive voltage state at the at least one input of the at least one ADC has been detected.

Abstract translation: 一种包括至少一个模数转换器的集成电路装置。 至少一个ADC包括可操作地耦合到集成电路器件的至少一个外部触点的至少一个输入。 集成电路装置还包括检测电路，其包括至少一个检测模块。 所述至少一个检测模块被布置为在其第一输入处接收所述至少一个ADC的至少一个输入端的电压电平的指示，将所接收的指示与阈值进行比较，并且如果所接收的指示超过 输出在至少一个ADC的至少一个输入处已经检测到过电压状态的指示。

公开(公告)号：US09952922B2

公开(公告)日：2018-04-24

申请号：US14899595

申请日：2013-07-18

Applicant: Graham Edmiston ,  Alan Devine ,  David McMenamin ,  Andrew Roberston ,  James Andrew Collier Scobie

Inventor： Graham Edmiston ,  Alan Devine ,  David McMenamin ,  Andrew Roberston ,  James Andrew Collier Scobie

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/28

CPC classification number: G06F11/079 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/28

Abstract: Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

公开(公告)号：US09846663B2

公开(公告)日：2017-12-19

申请号：US14778115

申请日：2013-03-22

Applicant: Alistair Roberston ,  Carl Culshaw ,  Alan Devine

Inventor： Alistair Roberston ,  Carl Culshaw ,  Alan Devine

IPC: G06F13/28 ,  G06F13/364 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/364 ,  G06F13/4282

Abstract: A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described.

公开(公告)号：US09190989B1

公开(公告)日：2015-11-17

申请号：US14509046

申请日：2014-10-07

Applicant: Garima Sharda ,  Carl Culshaw ,  Alan Devine ,  Akshay K. Pathak ,  Alistair P. Robertson

Inventor： Garima Sharda ,  Carl Culshaw ,  Alan Devine ,  Akshay K. Pathak ,  Alistair P. Robertson

IPC: G05F1/10 ,  H03K3/012 ,  G05F1/66

CPC classification number: G06F1/3293 ,  G05F1/66 ,  G06F1/3287 ,  H03K3/012 ,  Y02D10/122 ,  Y02D10/171

Abstract: A power management system permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off. The power management system supports asynchronous domains with common shared peripherals. The asynchronous domains operate as a single entity while in a full power mode with the peripheral and system resources being shared. The system can be used in automotive systems where most of the system is power-gated leaving just a power regulator controller, some counters and an input/output segment alive for wakeup purposes.

Abstract translation: 电源管理系统允许小型微控制器子系统或低功率域在主子系统域从上电循环到关闭时连续运行。 电源管理系统支持具有通用共享外设的异步域。 异步域作为单个实体运行，而处于全功率模式，外围设备和系统资源共享。 该系统可用于汽车系统，其中大多数系统是电源门控，只剩下一个电源调节器控制器，一些计数器和一个输入/输出段，用于唤醒目的。

公开(公告)号：US20150248358A1

公开(公告)日：2015-09-03

申请号：US14194862

申请日：2014-03-03

Applicant: MICHAEL JOHNSTON ,  ALAN DEVINE ,  ALISTAIR PAUL ROBERTSON ,  MANFRED THANNER

Inventor： MICHAEL JOHNSTON ,  ALAN DEVINE ,  ALISTAIR PAUL ROBERTSON ,  MANFRED THANNER

IPC: G06F12/14

CPC classification number: G06F12/1475 ,  G06F12/0284 ,  G06F12/1441 ,  G06F15/7807 ,  G06F21/00 ,  G06F21/52 ,  G06F21/71 ,  G06F2212/1052

Abstract: A system on chip, comprising a processing unit for executing processes, a memory unit, and a memory control unit connected between the processing unit and the memory unit, is described. The memory control unit allocates a memory region to a process. The memory control unit comprises a process activity counter which counts a duration of the process or transactions by the process to or from the memory region and which maintains a process activity count representing the counted duration of the process or the counted transactions to or from the memory region. The memory control unit disables the memory region in response to the process activity count exceeding a maximum process activity count. Notably, it blocks the memory region against further transactions by the process and against transactions by any other processes.A method of operating a system on chip is also described.

Abstract translation: 一种片上系统，包括用于执行处理的处理单元，存储单元和连接在处理单元和存储单元之间的存储器控​​制单元。 存储器控制单元向进程分配存储区域。 存储器控制单元包括处理活动计数器，其通过进入存储器区域或从存储器区域的处理对进程或事务的持续时间进行计数，并且维护表示处理的计数持续时间的处理活动计数或来自存储器的计数事务 地区。 存储器控制单元响应于超过最大过程活动计数的过程活动计数而禁用存储器区域。 值得注意的是，它会阻止内存区域进一步的进程交易和任何其他进程的事务处理。 还描述了一种操作片上系统的方法。

公开(公告)号：US09118179B2

公开(公告)日：2015-08-25

申请号：US13880193

申请日：2010-11-22

Applicant: Alistair Robertson ,  Carl Culshaw ,  Alan Devine

Inventor： Alistair Robertson ,  Carl Culshaw ,  Alan Devine

IPC: H02H3/20 ,  G01R19/00 ,  H03M1/12 ,  G01R19/165

CPC classification number: H02H3/20 ,  G01R19/0084 ,  G01R19/165 ,  H03M1/12 ,  H03M1/129

Abstract: An integrated circuit device comprising at least one analog to digital converter. The at least one ADC comprises at least one input operably coupled to at least one external contact of the integrated circuit device. The integrated circuit device further comprises detection circuitry comprising at least one detection module. The at least one detection module being arranged to receive at a first input thereof an indication of a voltage level at the at least one input of the at least one ADC, compare the received indication to a threshold value, and if the received indication exceeds the threshold value, output an indication that an excessive voltage state at the at least one input of the at least one ADC has been detected.

Abstract translation: 一种包括至少一个模数转换器的集成电路装置。 至少一个ADC包括可操作地耦合到集成电路器件的至少一个外部触点的至少一个输入。 集成电路装置还包括检测电路，其包括至少一个检测模块。 所述至少一个检测模块被布置为在其第一输入处接收所述至少一个ADC的至少一个输入端的电压电平的指示，将所接收的指示与阈值进行比较，并且如果所接收的指示超过 输出在至少一个ADC的至少一个输入处已经检测到过电压状态的指示。

公开(公告)号：US08543860B2

公开(公告)日：2013-09-24

申请号：US13059246

申请日：2008-08-26

Applicant: Derek Beattie ,  Carl Culshaw ,  Alan Devine ,  James Andrew Collier Scobie

Inventor： Derek Beattie ,  Carl Culshaw ,  Alan Devine ,  James Andrew Collier Scobie

IPC: G06F1/04 ,  G06F1/00 ,  G06F15/00 ,  G06F11/00

CPC classification number: G06F1/04

Abstract: A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.

Abstract translation: 时钟系统包括多个时钟数据处理装置和时钟控制电路，时钟控制电路控制多个时钟信号的产生以及时钟信号到多个数据处理装置的应用，允许对数据中的至少一个进行时钟 处理设备，同时冻结所有数据处理设备中的至少一个。 一种用于计时多个时钟数据处理装置的方法包括：控制多个时钟信号的产生并控制对多个数据处理装置的时钟信号的应用，允许在冻结期间对数据处理装置中的至少一个进行计时 所有这些数据处理设备中的至少一个。