公开(公告)号：US20100156944A1

公开(公告)日：2010-06-24

申请号：US12317119

申请日：2008-12-19

申请人： Frank Haupt ,  David R. Baum

发明人： Frank Haupt ,  David R. Baum

IPC分类号： G09G5/10 ,  G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2320/0673 ,  G09G2330/021

摘要： Gamma curve correction circuitry includes first (24-1,2 . . . 11) and second (24-12,13 . . . 22) groups of gamma correction buffers and corresponding DACs (28-1,2 . . . 22). Each buffer has an input coupled to an output of a corresponding DAC, respectively, and an output coupled by a corresponding output conductor, respectively, to a corresponding resistor string tap point. A midrange voltage (V30) is produced with a value approximately midway between a first voltage (VDD) and a second voltage (GND) and is coupled to provide power to the first and second groups of buffers. The first voltage is coupled to a first voltage terminal of a first buffer (24-11) of the first group. A second voltage terminal of the first buffer is coupled to the midrange voltage. The midrange voltage is coupled to a first voltage terminal of a first buffer (24-12) of the second group. A second voltage terminal of the first buffer of the second group is coupled to the second voltage.

摘要翻译： 伽马曲线校正电路包括第一（24-1,2.1,11）和第二（24-12,13 ...）组伽马校正缓冲器和相应的DAC（28-1,2 ... 22）。 每个缓冲器分别具有耦合到对应的DAC的输出的输入端和由相应的输出导体分别耦合到对应的电阻器串点的输出端。 产生中间电压（V30），其值大约在第一电压（VDD）和第二电压（GND）之间的中间，并被耦合以向第一和第二组缓冲器提供电力。 第一电压耦合到第一组的第一缓冲器（24-11）的第一电压端子。 第一缓冲器的第二电压端子耦合到中频电压。 中间电压耦合到第二组的第一缓冲器（24-12）的第一电压端子。 第二组的第一缓冲器的第二电压端子耦合到第二电压。

公开(公告)号：US06437645B1

公开(公告)日：2002-08-20

申请号：US09784724

申请日：2001-02-15

申请人： Vadim V. Ivanov ,  David R. Baum

发明人： Vadim V. Ivanov ,  David R. Baum

IPC分类号： H03F345

CPC分类号： H03F3/45372 ,  H03F3/3028 ,  H03F3/45192 ,  H03F3/45269 ,  H03F3/45273 ,  H03F3/45291 ,  H03F3/45367 ,  H03F2200/331 ,  H03F2203/30084 ,  H03F2203/30096 ,  H03F2203/30117 ,  H03F2203/30129 ,  H03F2203/30151 ,  H03F2203/30156 ,  H03K17/04106

摘要： A differential input circuit (1) includes circuitry for generating slew boost currents to be supplied to an output stage of an operational amplifier. The differential input circuit (1) includes a differential current steering circuit including a first transistor (M2) having a gate coupled to receive a first input signal (Vin−), a second transistor (M3) having a gate coupled to receive a second input signal (Vin+), and a constant current source (20) coupled to sources of the first and second transistors, and providing first (4 or 6) and second (5 or 7) outputs of the differential input circuit coupled to the first (M2) and second (M3), respectively. A first slew current circuit is operated in response to the first input signal (Vin−) to produce a first slew boost current which is introduced into a current summing conductor (9) coupled to the sources of the first (M2) and second (M3) transistors and the constant current source (20). A second slew current circuit is operated in response to the second input signal (Vin+) to produce a second slew boost current which is introduced into the current summing conductor (9), wherein the first and second slew boost currents boosting currents flow through the second (M3) and first (M2) transistors, respectively.

摘要翻译： 差分输入电路（1）包括用于产生要提供给运算放大器的输出级的转换升压电流的电路。 差分输入电路（1）包括差动电流控制电路，其包括具有耦合以接收第一输入信号（Vin-）的栅极的第一晶体管（M2），第二晶体管（M3），其栅极耦合以接收第二输入 信号（Vin +）和耦合到第一和第二晶体管的源极的恒流源（20），以及提供耦合到第一（M2）的差分输入电路的第一（4或6）和第二（5或7） ）和第二（M3）。 响应于第一输入信号（Vin-）操作第一回转电流电路以产生第一压摆升压电流，其被引入耦合到第一（M2）和第二（M2）的源极的电流求和导体（9） ）晶体管和恒流源（20）。 响应于第二输入信号（Vin +）操作第二回转电流电路以产生被引入到电流求和导体（9）中的第二压摆升压电流，其中第一和第二压摆升压电流升压电流流过第二 （M3）和第一（M2）晶体管。

公开(公告)号：US08610658B2

公开(公告)日：2013-12-17

申请号：US12317119

申请日：2008-12-19

申请人： Frank Haupt ,  David R. Baum

发明人： Frank Haupt ,  David R. Baum

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2320/0673 ,  G09G2330/021

摘要： Gamma curve correction circuitry includes first (24-1,2 . . . 11) and second (24-12,13 . . . 22) groups of gamma correction buffers and corresponding DACs (28-1,2 . . . 22). Each buffer has an input coupled to an output of a corresponding DAC, respectively, and an output coupled by a corresponding output conductor, respectively, to a corresponding resistor string tap point. A midrange voltage (V30) is produced with a value approximately midway between a first voltage (VDD) and a second voltage (GND) and is coupled to provide power to the first and second groups of buffers. The first voltage is coupled to a first voltage terminal of a first buffer (24-11) of the first group. A second voltage terminal of the first buffer is coupled to the midrange voltage. The midrange voltage is coupled to a first voltage terminal of a first buffer (24-12) of the second group. A second voltage terminal of the first buffer of the second group is coupled to the second voltage.

摘要翻译： 伽马曲线校正电路包括第一（24-1,2.1,11）和第二（24-12,13 ...）组伽马校正缓冲器和相应的DAC（28-1,2 ... 22）。 每个缓冲器分别具有耦合到对应的DAC的输出的输入端和由相应的输出导体分别耦合到对应的电阻器串点的输出端。 产生中间电压（V30），其值大约在第一电压（VDD）和第二电压（GND）之间的中间，并被耦合以向第一和第二组缓冲器提供电力。 第一电压耦合到第一组的第一缓冲器（24-11）的第一电压端子。 第一缓冲器的第二电压端子耦合到中频电压。 中间电压耦合到第二组的第一缓冲器（24-12）的第一电压端子。 第二组的第一缓冲器的第二电压端子耦合到第二电压。

公开(公告)号：US5320538A

公开(公告)日：1994-06-14

申请号：US950114

申请日：1992-09-23

申请人： David R. Baum

发明人： David R. Baum

IPC分类号： G09B9/16 ,  G09B9/22 ,  G09B9/30 ,  H04N13/00 ,  G09B5/00

CPC分类号： H04N13/0278 ,  G09B9/165 ,  G09B9/22 ,  G09B9/307 ,  H04N13/044 ,  H04N13/0289 ,  H04N13/0468 ,  Y10S345/952

摘要： The system includes a computer (20), a detector (40) for detecting and tracking head orientation and head movement of an individual, a pair of tactile gloves (42, 44) which are donned by the individual (51) for detecting and transmitting to the computer (20) as input data orientation and movements of the hands of the individual inserted in the tactile gloves (42, 44), a stereoscopic, head-mounted display (31), a subsystem for enabling the computer to generate a stereoscopic image of the training environment, a subsystem for causing the stereoscopic image of the training environment to be displayed and changed by the computer relative to input data received by the computer relating to the head orientation and head movement of the individual, relative to input data received by the computer relating to orientation and movement of the hands of the individual inserted in the tactile gloves, and relative to input data reflecting realistic changes in the training environment that would be perceived by the individual if interacting with an identical, non-simulated, training environment. An object (43) representative of a tool is adapted for transmitting tactile information to the computer (20). Sounds representative of the environment are transmitted to the individual (51) through the earphones (33). Vocal emanations of the individual are detected by a microphone (48). System peripheral items (31, 33, 40, 42, 43, 44, 48) are connected to the computer (20) by means of wires (60, 61, 62, 63, 64, 65). The computer (20) interfaces and incorporates an environment simulation and modeling subsystem (22), an image generation component (24), a user interface management component (26), and a component for formulating and transmitting instructional input (28).

摘要翻译： 该系统包括计算机（20），用于检测和跟踪个体的头部取向和头部移动的检测器（40），由个体（51）穿过的用于检测和发送的一对触觉手套（42,44） 作为输入数据取向和插入在触觉手套（42,44）中的个体的手的移动的立体，头戴显示器（31）的计算机（20），用于使计算机能够产生立体感的子系统 训练环境的图像，用于使计算机相对于所接收到的输入数据相对于计算机接收到的与头部朝向和头部移动相关的输入数据显示和改变训练环境的立体图像的子系统 通过计算机关于插入在触觉手套中的个人的手的取向和移动以及反映将被训练的训练环境中的实际变化的输入数据 如果与相同的，非模拟的培训环境相互作用，则由个体接管。 代表工具的物体（43）适于将触觉信息传送到计算机（20）。 通过耳机（33）将代表环境的声音传送给个人（51）。 个人的声音发声由麦克风（48）检测。 系统周边物品（31,33,40,42,43,44,48）通过电线（60,61,62,63,64,65）连接到计算机（20）。 计算机（20）接口并且包括环境模拟和建模子系统（22），图像生成组件（24），用户界面管理组件（26）和用于制定和传送教学输入（28）的组件。

公开(公告)号：US06917084B2

公开(公告)日：2005-07-12

申请号：US10656451

申请日：2003-09-05

申请人： David R. Baum ,  Rodney T. Burt

发明人： David R. Baum ,  Rodney T. Burt

IPC分类号： H01L27/02 ,  H03F3/30

CPC分类号： H03F3/3061 ,  H01L27/0207 ,  H03F2200/366

摘要： A complementary output stage in integrated circuit includes a P-channel transistor (MP1) the segmented into a first group of sections (MP1-1,2 . . . 12) and an N-channel transistor (MN1) segmented into a second group of sections (MN1-1,2 . . . 12). The sections of the first group are disposed in a plurality of N-type well regions (35), respectively, and the sections of the second group are disposed in a plurality of P-type well regions (36), respectively. The sections of the first group are alternately located with respect to the sections of the second group so as to form an interdigitated output stage area of the integrated circuit including the P-channel transistor (MP1) and the N-channel transistor (MN1) so that the higher amount of heat normally generated in the N-channel transistor is dissipated over the entire interdigitated output stage area and reduces peak temperatures in the N-channel transistor.

摘要翻译： 集成电路中的互补输出级包括分段成第一组部分（MP1-1.2,12）和N沟道晶体管（MN 1）的P沟道晶体管（MP 1），其被分段成 第二组（MN 1 - 1,2。。12）。 第一组的部分分别设置在多个N型阱区（35）中，第二组的部分分别设置在多个P型阱区域（36）中。 第一组的部分相对于第二组的部分交替地定位，以便形成包括P沟道晶体管（MP 1）和N沟道晶体管（MN 1）的集成电路的交错输出级区域 ），使得在N沟道晶体管中通常产生的较高的热量在整个交叉输出级区域上消散，并降低N沟道晶体管中的峰值温度。

公开(公告)号：US06807040B2

公开(公告)日：2004-10-19

申请号：US09839981

申请日：2001-04-19

申请人： Vadim V. Ivanov ,  David R. Baum

发明人： Vadim V. Ivanov ,  David R. Baum

IPC分类号： H02H908

CPC分类号： H03K17/0822 ,  H03F1/523

摘要： Over-current protection is accomplished in an output transistor (MP) of an electronic circuit wherein an input signal (Vgatedrive) Is Applying to a first conductor (19) coupled to a gate of the output transistor to cause an output current (Iout) to flow through the output transistor and an output terminal (11) of the electronic circuit. A limit voltage (VLIMIT) who is applied to an input (21) of a voltage clamping circuit (18) to cause a clamping current to flow in the first conductor (19) as needed to prevent the magnitude of the input signal (Vgatedrive) from being less than the magnitude of the limit voltage (VLIMIT) so that the output current (Iout) is limited to a maximum current limit determined by the limit voltage (VLIMIT). A control signal (ILIMIT/n) is applied to an input of a current-to-voltage conversion circuit (20) to cause the current-to-voltage conversion circuit to produce the limit voltage (VLIMIT), which is applied to an emitter of a first transistor (Q1) having a collector in base connected to a bias current source (I1). The resulting voltage on a base of the first transistor is applied to a base of a second transistor (Q2), and the input signal (Vgatedrive) is applied to the first conductor (19).

摘要翻译： 过电流保护在电子电路的输出晶体管（MP）中完成，其中输入信号（Vgatedrive）施加到耦合到输出晶体管的栅极的第一导体（19），以使输出电流（Iout） 流过输出晶体管和电子电路的输出端子（11）。 施加到电压钳位电路（18）的输入（21）的限制电压（VLIMIT），以根据需要使钳位电流流过第一导体（19），以防止输入信号（Vgatedrive）的幅度， 从小于限制电压（VLIMIT）的幅度，使得输出电流（Iout）被限制为由极限电压（VLIMIT）确定的最大电流限制。 控制信号（ILIMIT / n）被施加到电流 - 电压转换电路（20）的输入，以使得电流 - 电压转换电路产生施加到发射极的极限电压（VLIMIT） 具有与偏置电流源（I1）连接的基极集电极的第一晶体管（Q1）。 将第一晶体管的基极上产生的电压施加到第二晶体管（Q2）的基极，并将输入信号（Vgatedrive）施加到第一导体（19）。

公开(公告)号：US20090174479A1

公开(公告)日：2009-07-09

申请号：US12287762

申请日：2008-10-14

申请人： Shoubao Yan ,  Gerald W. Steele ,  David R. Baum

发明人： Shoubao Yan ,  Gerald W. Steele ,  David R. Baum

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F1/0216 ,  H03F3/387 ,  H03F3/393 ,  H03F3/45219 ,  H03F3/45632 ,  H03F3/45928 ,  H03F2200/513

摘要： A differential amplifier (1D) includes circuitry (5,R1,R2,52) coupling a common mode component of an input voltage (Vin+−Vin−) to a maximum voltage selector circuit (53) that produces an internal voltage (VRAIL-TOP) equal to the larger of a first supply voltage (VREG) and the common mode component. An input amplifier circuit (46) of the differential amplifier is powered by the internal voltage. The input voltage (Vin+−Vin−) is coupled to inputs (41A,B) of the input amplifier circuit (46). Outputs (64A,B) of the input amplifier circuit (46) are amplified by an output amplifier (50).

摘要翻译： 差分放大器（1D）包括将输入电压（Vin + -Vin-）的共模分量耦合到产生内部电压的最大电压选择电路（53）的电路（5，R1，R2,52）（VRAIL-TOP ）等于第一电源电压（VREG）和共模分量中较大者。 差分放大器的输入放大器电路（46）由内部电压供电。 输入电压（Vin + -Vin-）耦合到输入放大器电路（46）的输入（41A，B）。 输入放大器电路（46）的输出（64A，B）由输出放大器（50）放大。

公开(公告)号：US07821333B2

公开(公告)日：2010-10-26

申请号：US12287762

申请日：2008-10-14

申请人： Shoubao Yan ,  Gerald W. Steele ,  David R. Baum

发明人： Shoubao Yan ,  Gerald W. Steele ,  David R. Baum

IPC分类号： H03F1/02

CPC分类号： H03F3/45475 ,  H03F1/0216 ,  H03F3/387 ,  H03F3/393 ,  H03F3/45219 ,  H03F3/45632 ,  H03F3/45928 ,  H03F2200/513

摘要： A differential amplifier (1D) includes circuitry (5,R1,R2,52) coupling a common mode component of an input voltage (Vin+−Vin−) to a maximum voltage selector circuit (53) that produces an internal voltage (VRAIL-TOP) equal to the larger of a first supply voltage (VREG) and the common mode component. An input amplifier circuit (46) of the differential amplifier is powered by the internal voltage. The input voltage (Vin+−Vin−) is coupled to inputs (41A,B) of the input amplifier circuit (46). Outputs (64A,B) of the input amplifier circuit (46) are amplified by an output amplifier (50).

摘要翻译： 差分放大器（1D）包括将输入电压（Vin + -Vin-）的共模分量耦合到产生内部电压的最大电压选择电路（53）的电路（5，R1，R2,52）（VRAIL-TOP ）等于第一电源电压（VREG）和共模分量中较大者。 差分放大器的输入放大器电路（46）由内部电压供电。 输入电压（Vin + -Vin-）耦合到输入放大器电路（46）的输入（41A，B）。 输入放大器电路（46）的输出（64A，B）由输出放大器（50）放大。

公开(公告)号：US07554517B2

公开(公告)日：2009-06-30

申请号：US11079357

申请日：2005-03-14

申请人： David R. Baum ,  Frank Haupt ,  Jerry L. Doorenbos

发明人： David R. Baum ,  Frank Haupt ,  Jerry L. Doorenbos

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3648 ,  G09G2320/0276 ,  G09G2320/04

摘要： A gamma reference voltage generator (10B) for an LCD display includes a control interface logic circuit (48) having an output bus coupled to inputs of a first register (46) having outputs coupled to inputs of a second register (42) the outputs of which are coupled to corresponding inputs of plurality of DACs (28). The control interface logic circuit receives gray scale codes representative of gamma reference voltages and transfers the codes via the output bus into the first register and controls further transfer of the codes to inputs of the DACs to instantaneously or rapidly update gamma correction voltages applied to the LCD display.

摘要翻译： 用于LCD显示器的伽马参考电压发生器（10B）包括控制接口逻辑电路（48），其具有耦合到具有耦合到第二寄存器（42）的输入的输出的第一寄存器（46）的输入的输出总线， 其耦合到多个DAC（28）的相应输入端。 控制接口逻辑电路接收代表伽马参考电压的灰度代码，并将代码经由输出总线传送到第一寄存器中，并控制进一步传输代码到DAC的输入端以瞬时或快速更新施加到LCD的伽马校正电压 显示。

公开(公告)号：US07271663B2

公开(公告)日：2007-09-18

申请号：US11210036

申请日：2005-08-23

申请人： David R. Baum ,  Vadim V. Ivanov

发明人： David R. Baum ,  Vadim V. Ivanov

IPC分类号： H03F1/22

CPC分类号： H03F3/45309 ,  H03F3/3028

摘要： An operational amplifier includes an input stage for producing a voltage signal in response to an input signal. An output stage includes an output transistor having a source coupled to a supply voltage and a gate coupled to receive the voltage signal. An output cascode transistor has a source coupled to a drain of the output transistor and a drain coupled to an output conductor. A gate control amplifier includes an input stage including a first input transistor having a control electrode coupled to the source of the output cascode transistor and an active load transistor, the input transistor and the active load transistor being coupled to a gate of the output cascode transistor. The gate control amplifier also includes a feedback amplifier having an input coupled to the source of the output cascode transistor and an output coupled to a control electrode of the active load transistor.

摘要翻译： 运算放大器包括用于响应于输入信号产生电压信号的输入级。 输出级包括具有耦合到电源电压的源极的输出晶体管和耦合以接收电压信号的栅极。 输出共源共栅晶体管具有耦合到输出晶体管的漏极的源极和耦合到输出导体的漏极。 栅极控制放大器包括输入级，其包括具有耦合到输出共源共栅晶体管的源极的控制电极和有源负载晶体管的第一输入晶体管，输入晶体管和有源负载晶体管耦合到输出共源共栅晶体管的栅极 。 栅极控制放大器还包括反馈放大器，其具有耦合到输出共源共栅晶体管的源极的输入端和耦合到有源负载晶体管的控制电极的输出端。