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公开(公告)号：US5521789A
公开(公告)日：1996-05-28
申请号：US213661
申请日：1994-03-15
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An enhanced bipolar-transistor apparatus for protecting electronic devices from electrostatic discharge damage. The apparatus is built around a bipolar transistor coupled between a power rail and the circuit to be protected. The protection is based on the high-current-capacity path through the bipolar transistor which is opened up either by collector-to-emitter punch-through in the bipolar transistor or by the bipolar transistor going into normal conduction upon being turned on by a switch coupled to the base of the bipolar transistor. In the preferred embodiment the switch is a MOS transistor that is designed to undergo source-to-drain breakdown at a fixed threshold voltage, whereupon it activates the bipolar transistor which in turn discharges the overvoltage. In this way the advantages of the high-current-capacity bipolar transistor are obtained without the concern that fabrication vagaries will prevent the bipolar transistor from providing needed protection, such as is the situation where the punch-through phenomenon alone is relied on.
摘要翻译： 一种用于保护电子器件免受静电放电损坏的增强型双极晶体管装置。 该装置围绕耦合在电源轨和待保护电路之间的双极晶体管构成。 该保护基于通过双极晶体管的大电流容量路径，其通过双极晶体管中的集电极到发射极穿通而被双极晶体管打开，或者通过由开关导通的双极晶体管进入正常导通 耦合到双极晶体管的基极。 在优选实施例中，开关是被设计成在固定阈值电压下经历源极到漏极击穿的MOS晶体管，于是它激活双极晶体管，该双极晶体管又导通过电压。 以这种方式，可以获得大电流双极晶体管的优点，而不用担心制造变形会阻止双极晶体管提供所需的保护，例如仅依靠穿通现象的情况。
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公开(公告)号：US5233237A
公开(公告)日：1993-08-03
申请号：US803466
申请日：1991-12-06
IPC分类号： H03K17/16 , H03K17/567 , H03K19/003 , H03K19/08 , H03K19/088 , H03K19/0944
CPC分类号： H03K19/00361 , H03K19/09448
摘要： A BICMOS output buffer circuit delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). A CMOS output pulldown driver transistor (Q60) sources base drive current to a relatively large current conducting bipolar primary output pulldown transistor (Q44). A relatively small current conducting CMOS secondary output pulldown transistor (Q60A) is coupled with primary current path in parallel with the primary current path of the bipolar primary output pulldown transistor (Q44) between the output (V.sub.OUT) and low potential power rail (GNDN). The control gate node of CMOS secondary output pulldown transistor (Q60A) is coupled to the control gate node of the CMOS output pulldown driver transistor (Q60) to initiate pulldown of a small sinking current before turn on of the bipolar primary output pulldown transistor (Q44) to reduce the maximum peak output noise (V.sub.OLP). A feed forward circuit capacitance is coupled between the control gate node of the CMOS output pulldown driver transistor (Q60) and base node of the bipolar output pulldown transistor (Q 44). The capacitance value is selected to pass a transient capacitive current sufficient for early turn on of the bipolar output pulldown transistor before the CMOS output pulldown driver transistor delivers sustained conduction current to reduce the maximum "valley" output noise (V.sub.OLV).
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公开(公告)号：US5204554A
公开(公告)日：1993-04-20
申请号：US802747
申请日：1991-12-06
IPC分类号： H01L23/50 , H01L21/822 , H01L27/04 , H03K17/16 , H03K19/00 , H03K19/003
CPC分类号： H03K19/00346 , H03K17/16 , H01L2224/48091 , H01L2224/49175 , H01L2924/1305 , H01L2924/3011
摘要： An output buffer circuit (10) delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). The output buffer circuit comprises an input stage (12) coupled between a relatively quiet power supply rail (V.sub.CCQ) and a relatively quiet power ground rail (GNDQ), and an output stage (14) coupled between a relatively noisy power supply rail (V.sub.CCN) and a relatively noisy power ground rail (GNDN). A first coupling resistor (R5) is coupled between the relatively quiet and noisy supply rails (V.sub.CCQ, V.sub.CCN) for reducing V.sub.CC droop in the relatively noisy supply rail (V.sub.CCN) which in turn reduces output step in voltage during transition from low to high potential level (LH) at the output (V.sub.OUT). A second coupling resistor (R5A) is coupled between the relatively quiet and noisy ground rails (GNDQ,GNDN). The coupling resistors (R5 and R5A) have low resistance values selected for partially coupling the supply and ground rails respectively, while maintaining partial isolation for protecting input dynamic threshold levels of quiet outputs. The first coupling resistor (R5) is coupled between supply rail bond pads (20,22), while the second coupling resistor (R5A) is coupled between ground rail bond pads (30,32). The power rail bond pads (20,22) (30,32) are coupled respectively to split leads (24,25) (34,35) of a split lead leadframe merging respectively to a common V.sub.CC pin (28) and a common GND pin (38).
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