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1.发明申请公开(公告)号：US20250169121A1
公开(公告)日：2025-05-22
申请号：US18841302
申请日：2023-02-23
Applicant: Epinovatech AB
Inventor： Martin Andreas OLSSON
Abstract: The present inventive concept relates to a spin qubit transistor (100) comprising a base layer (102), a first qubit comprising, a first computing semiconductor island (106) and a first readout semiconductor island (108) arranged with a distance in the range of 3-10 nm therebetween, a second qubit comprising, a second computing semiconductor island (110) and a second readout semiconductor island (112) arranged with a distance in the range of 3-10 nm therebetween, wherein each of said semiconductor islands has a size causing each of said semiconductor islands to exhibit 3-dimensional quantum confinement of a single electron hole, and wherein each of said semiconductor islands forms a semiconductor heterojunction with the base layer. Each of the semiconductor islands has a corresponding gate (G1-G4), for modulation of the computing islands or readout of the readout islands. Said first computing semiconductor island and said second computing semiconductor island are configured to have a unique resonance frequency respectively. A control electrode arrangement (B) between the computing and the readout islands controls the coupling between the qubits. The present inventive concept further comprises a method for forming a spin qubit transistor and a quantum computer comprising at least one spin qubit transistor.
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公开(公告)号：US20250040175A1
公开(公告)日：2025-01-30
申请号：US18713120
申请日：2022-11-23
Applicant: Epinovatech AB
Inventor： Martin Andreas OLSSON
IPC: H01L29/778 , H01L21/02 , H01L27/095 , H01L29/15 , H01L29/20 , H01L29/66
Abstract: A vertical high-electron-mobility transistor, HEMT (100), comprising: a substrate (310); a drain contact (410), the drain contact being a metal contact via through said substrate; a pillar layer (500) arranged above the drain contact (410) and comprising at least one vertical pillar (510) and a supporting material (520) laterally enclosing the at least one vertical pillar (510); a heterostructure mesa (600) arranged on the pillar layer (500), the heterostructure mesa (600) comprising an AlGaN-layer (610) and a GaN-layer (620), together forming a heterojunction (630); at least one source contact (420a, 420b) electrically connected to the heterostructure mesa (600); a gate contact (430) arranged on said heterostructure mesa (600), and above the at least one vertical pillar (510); wherein the at least one vertical pillar (510) is forming an electron transport channel between the drain contact (410) and the heterojunction (630).
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公开(公告)号：US12148821B2
公开(公告)日：2024-11-19
申请号：US18321643
申请日：2023-05-22
Applicant: Epinovatech AB
Inventor： Martin Andreas Olsson
IPC: H01L29/20 , H01L29/04 , H01L29/06 , H01L29/205 , H01L29/66 , H01L29/778
Abstract: Apparatuses and methods relating to semiconductor layer structures are disclosed. A method for producing a semiconductor layer structure ay involve providing a Si substrate comprising a top surface, forming a first semiconductor layer on the substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures, arranged perpendicularly to the top surface of the substrate, the first semiconductor layer comprising AlN, and epitaxially growing a second semiconductor layer which laterally and vertically encloses the plurality of vertical nanowire structures thereby encapsulating dislocations in shells around the nanowires, wherein the second semiconductor layer comprises AlxGa1-xN, wherein 0≤x≤0.95.
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公开(公告)号：US12027989B2
公开(公告)日：2024-07-02
申请号：US17755142
申请日：2020-10-22
Applicant: Epinovatech AB
Inventor： Martin Andreas Olsson
IPC: H02M3/158 , B60L50/60 , B60L53/24 , H01L29/778 , H02J7/02 , H02M1/00 , H02M7/06 , H02M7/21 , H02M7/217 , H03K17/10 , H03K17/16
CPC classification number: H02M7/217 , B60L50/60 , B60L53/24 , H01L29/778 , H02J7/02 , H02M1/0048 , H02M3/158 , H02M7/06 , H02M7/21 , H03K17/102 , H03K17/163 , B60L2210/30 , B60L2210/40 , H01M2220/20 , H01M2220/30 , H02M1/0045 , H02M1/007
Abstract: There is provided an AC-DC converter circuit (100) for high power charging of an electrical battery. The circuit comprises an input rectifier comprising a first node and a second node. The input rectifier (110) is configured to receive an AC voltage at the first node (112) and provide a rectified voltage at the second node (114). The circuit further comprises a first transistor (120), comprising a first gate node (122), a first source node (124), and a first drain node (126). The first drain node is connected to the second node of the input rectifier. The first gate node is connected to a ground node (170). The circuit further comprises a second transistor (130), comprising a second gate node (132), a second source node (134), and a second drain node (136). The second drain node is connected to the first source node. The second transistor materially corresponds to the first transistor. The circuit further comprises a duty cycle control unit (140) connected to the second gate node for providing the second transistor with a switching waveform. The circuit further comprises an output rectifier (150) connected to the second source node or the first source node. The circuit further comprises an output electronic filter (160) connected to the second source node or an output node (151) of the output rectifier. An AC-DC converter device, a method for charging an electrical battery, and a regenerative braking system is also provided.
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公开(公告)号：US20220302293A1
公开(公告)日：2022-09-22
申请号：US17806400
申请日：2022-06-10
Applicant: Epinovatech AB
Inventor： Martin Andreas Olsson
IPC: H01L29/778 , H01L29/205 , H01L29/20 , H01L29/04 , H01L29/66 , H01L29/06
Abstract: There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising AlxGa1-xN, wherein 0≤x≤0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising AlyGa1-yN, wherein 0≤y≤0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.
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Patent Agency Ranking
公开(公告)号：US20210265632A1
公开(公告)日：2021-08-26
申请号：US17302907
申请日：2021-05-14
Applicant: Epinovatech AB
Inventor： Martin Andreas Olsson
Abstract: There is provided a solid-state battery layer structure which may include an anode current collector metal layer, an anode layer arranged on the anode current collector metal layer, a solid electrolyte layer arranged on the anode layer laterally, a cathode layer arranged on the solid electrolyte layer, and a cathode current collector metal layer, and a plurality of nanowire structures comprising silicon and/or gallium nitride, wherein said nanowire structures are arranged on the anode layer and, wherein said nanowire structures are laterally and vertically enclosed by the solid electrolyte layer, wherein the anode layer comprises silicon and a plurality of metal vias connecting the plurality of nanowire structures with the anode current collector metal layer. Methods for producing solid-state battery layer structures are also provided.
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公开(公告)号：US20240363693A1
公开(公告)日：2024-10-31
申请号：US18292860
申请日：2022-07-12
Applicant: Epinovatech AB
Inventor： Martin Andreas OLSSON
IPC: H01L29/201 , H01L21/02 , H01L27/092 , H01L29/20 , H01L29/66 , H01L29/775 , H01L29/78
CPC classification number: H01L29/201 , H01L21/0254 , H01L29/2003 , H01L27/0928 , H01L29/66477 , H01L29/775 , H01L29/78
Abstract: A transistor (1) comprising a source (10), a body (12) and a drain (14), the transistor (1) further comprising a plurality of semiconductor layers (20), wherein layers of the plurality of semiconductor layers (20) are made of AlGaN or GaN, and wherein the plurality of semiconductor layers (20) is configured such that an aluminum content changes between each consecutive layer such that every second layer has a lower aluminum content than the neighboring mutually opposite layers thereof, wherein the transistor (1) is either a N-channel metal-oxide-semiconductor, NMOS, transistor (1′), wherein part of the plurality of semiconductor layers (20) is p-doped and forms part of the body (12) of the NMOS transistor (1′); or a P-channel metal-oxide-semiconductor, PMOS, transistor (1″), wherein part of the plurality of semiconductor layers (20) is p-doped and forms part of the source (10) or the drain (14) of the PMOS transistor (1″).
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公开(公告)号：US20240356456A1
公开(公告)日：2024-10-24
申请号：US18761211
申请日：2024-07-01
Applicant: Epinovatech AB
Inventor： Martin Andreas Olsson
IPC: H02M7/217 , B60L50/60 , B60L53/24 , H01L29/778 , H02J7/02 , H02M1/00 , H02M3/158 , H02M7/06 , H02M7/21 , H03K17/10 , H03K17/16
CPC classification number: H02M7/217 , B60L50/60 , B60L53/24 , H01L29/778 , H02J7/02 , H02M1/0048 , H02M3/158 , H02M7/06 , H02M7/21 , H03K17/102 , H03K17/163 , B60L2210/30 , B60L2210/40 , H01M2220/20 , H01M2220/30 , H02M1/0045 , H02M1/007
Abstract: There is provided an AC-DC converter circuit (100) for high power charging of an electrical battery. The circuit comprises an input rectifier comprising a first node and a second node. The input rectifier (110) is configured to receive an AC voltage at the first node (112) and provide a rectified voltage at the second node (114). The circuit further comprises a first transistor (120), comprising a first gate node (122), a first source node (124), and a first drain node (126). The first drain node is connected to the second node of the input rectifier. The first gate node is connected to a ground node (170). The circuit further comprises a second transistor (130), comprising a second gate node (132), a second source node (134), and a second drain node (136). The second drain node is connected to the first source node. The second transistor materially corresponds to the first transistor. The circuit further comprises a duty cycle control unit (140) connected to the second gate node for providing the second transistor with a switching waveform. The circuit further comprises an output rectifier (150) connected to the second source node or the first source node. The circuit further comprises an output electronic filter (160) connected to the second source node or an output node (151) of the output rectifier. An AC-DC converter device, a method for charging an electrical battery, and a regenerative braking system is also provided.
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公开(公告)号：US20240250686A1
公开(公告)日：2024-07-25
申请号：US18629267
申请日：2024-04-08
Applicant: Epinovatech AB
Inventor： Martin Andreas Olsson
IPC: H03K19/17728 , H03K19/17736 , H03K19/1776
CPC classification number: H03K19/17728 , H03K19/17744 , H03K19/1776
Abstract: There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120) comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0
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公开(公告)号：US11955972B2
公开(公告)日：2024-04-09
申请号：US17905908
申请日：2021-03-10
Applicant: Epinovatech AB
Inventor： Martin Andreas Olsson
IPC: H03K19/17728 , H03K19/17736 , H03K19/1776
CPC classification number: H03K19/17728 , H03K19/17744 , H03K19/1776
Abstract: There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120) comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0
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