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    HEMT including MIS structure
    1.
    发明申请
    HEMT including MIS structure 审中-公开
    HEMT包括MIS结构

    公开(公告)号：US20080142845A1

    公开(公告)日：2008-06-19

    申请号：US12000528

    申请日：2007-12-13

    申请人： Masahito KODAMA ,  Eiko HAYASHI ,  Tsutomu UESUGI ,  Masahiro SUGIMOTO

    发明人： Masahito KODAMA ,  Eiko HAYASHI ,  Tsutomu UESUGI ,  Masahiro SUGIMOTO

    IPC分类号： H01L29/778

    CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/78 ,  H01L29/7827

    摘要： A HEMT has a drain region adapted to be electrically connected to a high voltage of an electric source, a source region adapted to be electrically connected to a low voltage of the electric source. A first semiconductor region is disposed between the drain region and the source region. A MIS structure and a heterostructure are disposed at a surface of the first semiconductor region. The MIS structure includes a gate electrode that faces a portion of a surface of the first semiconductor region with a gate insulating membrane therebetween. The heterostructure includes a second semiconductor region which makes contact with a rest portion of the surface of the first semiconductor region and has a wider band-gap than the first semiconductor region. The drain region and the source region are capable of being electrically connected with a structure in which the MIS structure 40 and the heterostructure are arranged in series.

    摘要翻译： HEMT具有适于电连接到电源的高电压的漏极区域，适于电连接到电源的低电压的源极区域。 第一半导体区域设置在漏极区域和源极区域之间。 MIS结构和异质结构设置在第一半导体区域的表面。 MIS结构包括栅电极，其面对第一半导体区域的表面的一部分，栅极绝缘膜在其间。 异质结构包括与第一半导体区域的表面的其余部分接触并且具有比第一半导体区域更宽的带隙的第二半导体区域。 漏极区域和源极区域能够与MIS结构40和异质结构串联布置的结构电连接。

    Group III nitride based semiconductor device having trench structure or mesa structure and production method therefor
    2.
    发明申请
    Group III nitride based semiconductor device having trench structure or mesa structure and production method therefor 审中-公开
    具有沟槽结构或台面结构的III族氮化物基半导体器件及其制造方法

    公开(公告)号：US20080105954A1

    公开(公告)日：2008-05-08

    申请号：US11976451

    申请日：2007-10-24

    申请人： Masahito KODAMA ,  Eiko HAYASHI ,  Masahiro SUGIMOTO

    发明人： Masahito KODAMA ,  Eiko HAYASHI ,  Masahiro SUGIMOTO

    IPC分类号： H01L29/06 ,  H01L21/306

    CPC分类号： H01L29/7813 ,  H01L21/32134 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/432 ,  H01L29/66734 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/8613 ,  H01L33/24 ,  H01L33/382 ,  H01S5/0421 ,  H01S5/32341

    摘要： A group III nitride based semiconductor device which has a trench or mesa structure and of which leakage of current and reduction of breakdown voltage are prevented. A GaN layer 2 was grown on a C-plane sapphire substrate 1, and a T-shaped USG film 3 was formed on the GaN layer 2 so that side surfaces of the USG film 3 were arranged parallel to A-plane and M-plane of the GaN layer 2. Thereafter, by using the USG film 3 as a mask, the GaN layer 2 was dry-etched. As is clear from FIGS. 2A and 2B, the M-plane is less roughened as compared with the A-plane. Subsequently, wet-etched was performed by use of an aqueous TMAH solution. As is clear from FIGS. 2C and 2D, roughness of the A-plane and the M-plane are removed, and, particularly, the M-plane assumes a mirror surface. Thus, through provision of M-plane side surfaces of a trench or an etching-formed mesa, leakage of current and reduction of breakdown voltage of a group III nitride based semiconductor device can be prevented.

    摘要翻译： 具有沟槽或台面结构，并且防止电流泄漏和击穿电压降低的III族氮化物基半导体器件。 在C面蓝宝石衬底1上生长GaN层2，在GaN层2上形成T形USG膜3，使得USG膜3的侧面平行于A面和M面 的GaN层2。 此后，通过使用USG膜3作为掩模，对GaN层2进行干式蚀刻。 从图 如图2A和2B所示，与A平面相比，M平面不那么粗糙。 随后，使用TMAH水溶液进行湿蚀刻。 从图 如图2C和2D所示，去除了A平面和M面的粗糙度，特别地，M平面呈现镜面。 因此，通过设置沟槽的M面侧面或蚀刻形成的台面，可以防止III族氮化物类半导体器件的漏电流和击穿电压的降低。

    Group III nitride based semiconductor and production method therefor
    4.
    发明授权
    Group III nitride based semiconductor and production method therefor 有权
    III族氮化物基半导体及其制备方法

    公开(公告)号：US07696071B2

    公开(公告)日：2010-04-13

    申请号：US11976450

    申请日：2007-10-24

    申请人： Masahito Kodama ,  Eiko Hayashi ,  Masahiro Sugimoto

    发明人： Masahito Kodama ,  Eiko Hayashi ,  Masahiro Sugimoto

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L21/02433 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265

    摘要： The invention provides a method for producing a group III nitride based semiconductor having a reduced number of crystal defects.A GaN layer 2 is epitaxially grown on a sapphire substrate 1 having C-plane as a main plane (FIG. 1A). Then, the layer is wet-etched by use of a 25% aqueous TMAH solution at 85° C. for one hour, to thereby form an etch pit 4 (FIG. 1B). Then, a GaN layer 5 is grown on the GaN layer 2 through the ELO method (FIG. 1C). The thus-formed GaN layer 5 has a screw dislocation density lower than that of the GaN layer 2.

    摘要翻译： 本发明提供一种具有减少晶体缺陷数的III族氮化物基半导体的制造方法。 在具有C面作为主平面的蓝宝石衬底1上外延生长GaN层2（图1A）。 然后，使用25％TMAH水溶液在85℃湿法蚀刻该层1小时，从而形成蚀刻坑4（图1B）。 然后，通过ELO方法在GaN层2上生长GaN层5（图1C）。 如此形成的GaN层5的螺旋位错密度低于GaN层2的位错密度。