公开(公告)号：US20080142845A1

公开(公告)日：2008-06-19

申请号：US12000528

申请日：2007-12-13

申请人： Masahito KODAMA ,  Eiko HAYASHI ,  Tsutomu UESUGI ,  Masahiro SUGIMOTO

发明人： Masahito KODAMA ,  Eiko HAYASHI ,  Tsutomu UESUGI ,  Masahiro SUGIMOTO

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/78 ,  H01L29/7827

摘要： A HEMT has a drain region adapted to be electrically connected to a high voltage of an electric source, a source region adapted to be electrically connected to a low voltage of the electric source. A first semiconductor region is disposed between the drain region and the source region. A MIS structure and a heterostructure are disposed at a surface of the first semiconductor region. The MIS structure includes a gate electrode that faces a portion of a surface of the first semiconductor region with a gate insulating membrane therebetween. The heterostructure includes a second semiconductor region which makes contact with a rest portion of the surface of the first semiconductor region and has a wider band-gap than the first semiconductor region. The drain region and the source region are capable of being electrically connected with a structure in which the MIS structure 40 and the heterostructure are arranged in series.

摘要翻译： HEMT具有适于电连接到电源的高电压的漏极区域，适于电连接到电源的低电压的源极区域。 第一半导体区域设置在漏极区域和源极区域之间。 MIS结构和异质结构设置在第一半导体区域的表面。 MIS结构包括栅电极，其面对第一半导体区域的表面的一部分，栅极绝缘膜在其间。 异质结构包括与第一半导体区域的表面的其余部分接触并且具有比第一半导体区域更宽的带隙的第二半导体区域。 漏极区域和源极区域能够与MIS结构40和异质结构串联布置的结构电连接。

公开(公告)号：US20080105954A1

公开(公告)日：2008-05-08

申请号：US11976451

申请日：2007-10-24

申请人： Masahito KODAMA ,  Eiko HAYASHI ,  Masahiro SUGIMOTO

发明人： Masahito KODAMA ,  Eiko HAYASHI ,  Masahiro SUGIMOTO

IPC分类号： H01L29/06 ,  H01L21/306

CPC分类号： H01L29/7813 ,  H01L21/32134 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/432 ,  H01L29/66734 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/8613 ,  H01L33/24 ,  H01L33/382 ,  H01S5/0421 ,  H01S5/32341

摘要： A group III nitride based semiconductor device which has a trench or mesa structure and of which leakage of current and reduction of breakdown voltage are prevented. A GaN layer 2 was grown on a C-plane sapphire substrate 1, and a T-shaped USG film 3 was formed on the GaN layer 2 so that side surfaces of the USG film 3 were arranged parallel to A-plane and M-plane of the GaN layer 2. Thereafter, by using the USG film 3 as a mask, the GaN layer 2 was dry-etched. As is clear from FIGS. 2A and 2B, the M-plane is less roughened as compared with the A-plane. Subsequently, wet-etched was performed by use of an aqueous TMAH solution. As is clear from FIGS. 2C and 2D, roughness of the A-plane and the M-plane are removed, and, particularly, the M-plane assumes a mirror surface. Thus, through provision of M-plane side surfaces of a trench or an etching-formed mesa, leakage of current and reduction of breakdown voltage of a group III nitride based semiconductor device can be prevented.

摘要翻译： 具有沟槽或台面结构，并且防止电流泄漏和击穿电压降低的III族氮化物基半导体器件。 在C面蓝宝石衬底1上生长GaN层2，在GaN层2上形成T形USG膜3，使得USG膜3的侧面平行于A面和M面 的GaN层2。 此后，通过使用USG膜3作为掩模，对GaN层2进行干式蚀刻。 从图 如图2A和2B所示，与A平面相比，M平面不那么粗糙。 随后，使用TMAH水溶液进行湿蚀刻。 从图 如图2C和2D所示，去除了A平面和M面的粗糙度，特别地，M平面呈现镜面。 因此，通过设置沟槽的M面侧面或蚀刻形成的台面，可以防止III族氮化物类半导体器件的漏电流和击穿电压的降低。

公开(公告)号：US20080105903A1

公开(公告)日：2008-05-08

申请号：US11976450

申请日：2007-10-24

申请人： Masahito KODAMA ,  Eiko HAYSASHI ,  Masahiro SUGIMOTO

发明人： Masahito KODAMA ,  Eiko HAYSASHI ,  Masahiro SUGIMOTO

IPC分类号： H01L29/205 ,  H01L29/20 ,  H01L21/20

CPC分类号： H01L21/02433 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265

摘要： The invention provides a method for producing a group III nitride based semiconductor having a reduced number of crystal defects. A GaN layer 2 is epitaxially grown on a sapphire substrate 1 having C-plane as a main plane (FIG. 1A). Then, the layer is wet-etched by use of a 25% aqueous TMAH solution at 85° C. for one hour, to thereby form an etch pit 4 (FIG. 1B) Then, a GaN layer 5 is grown on the GaN layer 2 through the ELO method (FIG. 1C). The thus-formed GaN layer 5 has a screw dislocation density lower than that of the GaN layer 2.

摘要翻译： 本发明提供一种具有减少晶体缺陷数的III族氮化物基半导体的制造方法。 在具有C面作为主平面的蓝宝石衬底1上外延生长GaN层2（图1A）。 然后，通过在85℃下使用25％TMAH水溶液湿法蚀刻该层1小时，从而形成蚀刻坑4（图1B）然后，在GaN上生长GaN层5 层2通过ELO方法（图1C）。 如此形成的GaN层5的螺旋位错密度低于GaN层2的位错密度。

公开(公告)号：US20120161154A1

公开(公告)日：2012-06-28

申请号：US13330835

申请日：2011-12-20

申请人： Tomohiro MIMURA ,  Shinichiro MIYAHARA ,  Hidefumi TAKAYA ,  Masahiro SUGIMOTO ,  Narumasa SOEJIMA ,  Tsuyoshi ISHIKAWA ,  Yukihiko WATANABE

发明人： Tomohiro MIMURA ,  Shinichiro MIYAHARA ,  Hidefumi TAKAYA ,  Masahiro SUGIMOTO ,  Narumasa SOEJIMA ,  Tsuyoshi ISHIKAWA ,  Yukihiko WATANABE

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7397

摘要： An SiC semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode and a drain electrode. The substrate has a Si-face as a main surface. The source region has the Si-face. The trench is provided from a surface of the source region to a portion deeper than the base region and extends longitudinally in one direction and has a Si-face bottom. The trench has an inverse tapered shape, which has a smaller width at an entrance portion than at a bottom, at least at a portion that is in contact with the base region.

摘要翻译： SiC半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极氧化膜，栅电极，源电极和漏电极。 基板具有作为主表面的Si面。 源区具有Si面。 沟槽从源极区域的表面提供到比基部区域更深的部分并且在一个方向上纵向延伸并且具有Si面底部。 沟槽具有倒锥形形状，至少在与基部区域接触的部分处，入口部分处的宽度比底部宽。

公开(公告)号：US20170084735A1

公开(公告)日：2017-03-23

申请号：US15365150

申请日：2016-11-30

申请人： Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Yuichi TAKEUCHI ,  Naohiro SUZUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66 ,  H01L29/417 ,  H01L29/872 ,  H01L29/15 ,  H01L21/761

CPC分类号： H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

公开(公告)号：US20140231827A1

公开(公告)日：2014-08-21

申请号：US14141174

申请日：2013-12-26

申请人： Yukihiko WATANABE ,  Sachiko AOI ,  Masahiro SUGIMOTO ,  Akitaka SOENO ,  Shinichiro MIYAHARA

发明人： Yukihiko WATANABE ,  Sachiko AOI ,  Masahiro SUGIMOTO ,  Akitaka SOENO ,  Shinichiro MIYAHARA

IPC分类号： H01L29/47 ,  H01L29/45 ,  H01L29/16 ,  H01L21/285 ,  H01L29/78

CPC分类号： H01L29/47 ,  H01L21/0485 ,  H01L21/28518 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7806 ,  H01L29/7813

摘要： A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.

摘要翻译： 一种制造半导体器件的方法包括：在碳化硅层的一个主表面上的第一区域中形成欧姆电极，将欧姆电极硅化，并在第二区域中形成肖特基电极 具有自对准的碳化硅层。 在没有形成欧姆电极的情况下暴露第二区域。

公开(公告)号：US20130330749A1

公开(公告)日：2013-12-12

申请号：US13968292

申请日：2013-08-15

申请人： Masahiro SUGIMOTO ,  Tomoyoshi SOGA

发明人： Tomoyoshi SOGA ,  Masahiro SUGIMOTO ,  Makoto SUEMATSU ,  Masashi HONMA ,  Takehito YAMAMOTO ,  Hiroshi SUZUKI

IPC分类号： G01N33/487 ,  G01N33/497

CPC分类号： G01N33/487 ,  C07K5/0215 ,  G01N33/497 ,  G01N33/576 ,  G01N33/6812 ,  G01N33/6893 ,  G01N2800/08 ,  G01N2800/60

摘要： A normal person (i.e. a control) and liver diseases such as drug induced liver injury, an asymptomatic hepatitis B carrier, an asymptomatic hepatitis C carrier, chronic hepatitis B, chronic hepatitis C, liver cancer, a nonalcoholic fatty liver disease (NAFLD), nonalcoholic steatohepatitis (NASH), and simple steatosis (SS) are identified by measuring the concentrations of γ-Glu-X (X represents an amino acid or an amine) peptides or the levels of AST or ALT in blood and carrying out, for example, a multiple logistic regression based on the measured value.

摘要翻译： 正常人（即对照）和肝脏疾病如药物诱发的肝损伤，无症状乙型肝炎携带者，无症状丙型肝炎携带者，慢性乙型肝炎，慢性丙型肝炎，肝癌，非酒精性脂肪性肝病（NAFLD） 通过测量血液中的γ-Glu-X（X代表氨基酸或胺）肽的浓度或AST或ALT的水平，进行例如，通过测定非酒精性脂肪性肝炎（NASH）和简单脂肪变性（SS） ，基于测量值的多重逻辑回归。

公开(公告)号：US20110291110A1

公开(公告)日：2011-12-01

申请号：US13117575

申请日：2011-05-27

申请人： Naohiro SUZUKI ,  Hideo MATSUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Jun MORIMOTO ,  Tsuyoshi ISHIKAWA ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

发明人： Naohiro SUZUKI ,  Hideo MATSUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Jun MORIMOTO ,  Tsuyoshi ISHIKAWA ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

IPC分类号： H01L29/12 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.

摘要翻译： 碳化硅半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极绝缘层，栅极电极，源极电极，漏极电极和深层。 深层设置在基底区域下方并且位于比沟槽更深的深度。 深层在与沟槽的纵向方向交叉的方向上分成多个部分。 这些部分包括设置在与沟槽相对应的位置处的一组部分，其在沟槽的纵向方向上以相等的间隔布置。 该组部分围绕沟槽的底部的角落。

公开(公告)号：US20100013006A1

公开(公告)日：2010-01-21

申请号：US12502251

申请日：2009-07-14

申请人： Masahiro SUGIMOTO ,  Tsutomu Uesugi ,  Masakazu Kanechika ,  Testsu Kachi

发明人： Masahiro SUGIMOTO ,  Tsutomu Uesugi ,  Masakazu Kanechika ,  Testsu Kachi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/8122 ,  H01L29/0623 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1037 ,  H01L29/1075 ,  H01L29/1079 ,  H01L29/42316 ,  H01L29/7828 ,  H01L29/7832 ,  H01L29/7838 ,  H01L29/812

摘要： A semiconductor device has a semiconductor substrate having a surface layer and a p-type semiconductor region, wherein the surface layer includes a contact region, a channel region and a drift region, the channel region is adjacent to and in contact with the contact region, the drift region is adjacent to and in contact with the channel region and includes n-type impurities at least in part, and the p-type semiconductor region is in contact with the drift region and at least a portion of a rear surface of the channel region, a main electrode disposed on the surface layer and electrically connected to the contact region, a gate electrode disposed on the surface layer and extending from above a portion of the contact region to above at least a portion of the drift region via above the channel region, and an insulating layer covering at least the portion of the contact region and not covering at least the portion of the drift region. The gate electrode and the contact region are insulated by the insulating layer, and the gate electrode and the drift region are in direct contact to form a Schottky junction.

摘要翻译： 半导体器件具有具有表面层和p型半导体区域的半导体衬底，其中表面层包括接触区域，沟道区域和漂移区域，沟道区域与接触区域相邻并与其接触， 漂移区域与沟道区域相邻并且与沟道区域接触并且至少部分地包括n型杂质，并且p型半导体区域与漂移区域和沟道的后表面的至少一部分接触 区域，设置在所述表面层上并电连接到所述接触区域的主电极，设置在所述表面层上并且从所述接触区域的一部分的上方延伸到所述漂移区域的至少一部分之上的栅电极， 以及至少覆盖所述接触区域的部分并且至少覆盖所述漂移区域的部分的绝缘层。 栅极电极和接触区域被绝缘层绝缘，栅电极和漂移区域直接接触形成肖特基结。

公开(公告)号：US20140319577A1

公开(公告)日：2014-10-30

申请号：US14244038

申请日：2014-04-03

申请人： Masahiro SUGIMOTO ,  Yuichi Takeuchi

发明人： Masahiro SUGIMOTO ,  Yuichi Takeuchi

IPC分类号： H01L29/739 ,  H01L29/66

CPC分类号： H01L29/7397 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7789

摘要： A semiconductor device disclosed in this specification includes a p+ contact region, an n+ source region, a p− base region, an n− drift region, a gate electrode, an insulator, a p+ electric field alleviating layer, and a p− positive hole extraction region. The electric field alleviating layer has same impurity concentration as the base region or higher, contacts a lower surface of the base region, and is formed in a same depth as the gate trench or in a position deeper than the gate trench. A positive hole extraction region extends to contact the electric field alleviating layer from a position to contact an upper surface of a semiconductor substrate or a first semiconductor region, and extracts a positive hole that is produced in the electric field alleviating layer at the avalanche breakdown to the upper surface of the semiconductor substrate.

摘要翻译： 在本说明书中公开的半导体装置包括p +接触区域，n +源极区域，基极区域，n漂移区域，栅电极，绝缘体，p +电场缓和层和ap-空穴提取区域 。 电场缓和层具有与基底区域相同的杂质浓度或更高的接触基底区域的下表面，并且形成在与栅极沟槽相同的深度或比栅极沟槽更深的位置。 正空穴提取区域延伸以从与半导体衬底或第一半导体区域的上表面接触的位置接触电场缓和层，并且在雪崩击穿时提取在电场减轻层中产生的正空穴 半导体衬底的上表面。