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1.发明授权公开(公告)号：US06169467A
公开(公告)日：2001-01-02
申请号：US09215856
申请日：1998-12-18
IPC分类号： H01P710
CPC分类号： H01P7/10
摘要： A TE0&ggr;&dgr; mode dielectric resonator (12) includes a cylindrical dielectric disk (32, 32′, 32″) having top and bottom ends (20, 22) spaced apart by a closed curve wall (24). The dielectric disk has an effective dielectric constant greater than 40. An axially aligned hole (36) is formed through the disk (32) between the top and bottom ends (20, 22). A conductive wall (34, 34″) is formed at or slightly beyond the wall (24) but does not cover the top and bottom ends (20, 22). The hole (36) has a preferred diameter between 0.21 and 0.4 times the diameter of the disk (32, 32′, 32″). The disk may be configured as a heterogeneous composite of dissimilar materials which exhibit increasing dielectric constant at increasing radial distance and increasing Q at decreasing radial distance.
摘要翻译： TE0gammadelta模式介质谐振器（12）包括具有由封闭曲线壁（24）间隔开的顶端和底端（20,22）的圆柱形电介质盘（32,32'，32“）。 电介质盘具有大于40的有效介电常数。在顶端和底端（20,22）之间通过盘（32）形成轴向对齐的孔（36）。 导电壁（34,34“）形成在壁（24）上或稍微超过壁（24），但不覆盖顶端和底端（20,22）。 孔（36）具有在盘（32,32'，32“）的直径的0.21和0.4倍之间的优选直径。 盘可以被配置为不同材料的异质复合材料，其在增加的径向距离处表现出增加的介电常数并且在径向距离减小时增加Q。
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公开(公告)号：US06301147B1
公开(公告)日：2001-10-09
申请号：US09520081
申请日：2000-03-08
IPC分类号： G11C1100
CPC分类号： H01L27/11 , G11C11/38 , G11C11/412 , H01L27/1104
摘要： A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (Vf) of the tunnel diode (32) controls the Vgs transfer curve (56) of the load transistor. The tunnel diode (32) may be formed at a junction between a mono-crystalline silicon layer (88) at a region (98, 100) which also serves as a source or drain of a transistor (36, 54) and a poly-crystalline silicon layer (106). The poly-crystalline silicon layer (106) also serves as a non-metallic, conductive interconnection (55) to save space.
摘要翻译： 静态RAM存储单元（30）使用交叉耦合增强模式，N沟道MOS驱动晶体管（36）形成双稳态触发器。 负载电路（34）耦合在驱动晶体管（36）和Vcc的I / O端口（40）之间。 对于每个驱动晶体管（36），负载电路包括耗尽模式N沟道MOS负载晶体管（54）和正向偏置隧道二极管（32）。 负载晶体管（54）的漏极和栅极耦合在隧道二极管（32）的阳极和阴极之间，使得隧道二极管（32）的正向电压（Vf）控制负载的Vgs转移曲线（56） 晶体管。 隧道二极管（32）可以形成在也用作晶体管（36,54）的源极或漏极的区域（98,100）处的单晶硅层（88）之间的结处， 晶体硅层（106）。 多晶硅层（106）还用作非金属导电互连（55）以节省空间。
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公开(公告)号：US06424227B1
公开(公告)日：2002-07-23
申请号：US09864097
申请日：2001-05-23
IPC分类号： H03F314
CPC分类号： H03F3/195 , H01L23/5227 , H01L23/66 , H01L2924/0002 , H01L2924/3011 , H03F3/26 , H03F2200/534 , H03F2200/541 , H01L2924/00
摘要： An integrated RF power amplifier 20 includes an on-chip input transformer (24) and an on-chip output transformer (28). Each of the transformers (24, 28) is formed from four spirals. Each primary winding (34, 42) and each secondary winding (38, 44) includes positive and negative spirals arranged so that positive current rotates in opposing rotational directions in the positive and negative spirals. The secondary winding (38) of the input transformer (24) and the primary winding (42) of the output transformer (28) each has a center tap (48, 50) located at the electrical and physical center of the winding. Positive and negative amplifiers (26) couple between the secondary winding of the input transformer (24) and the primary winding of the output transformer (28). DC biasing for the amplifiers (26) is provided through the positive and negative spirals of the center-tapped windings (38, 42) from the respective center taps (48, 50).
摘要翻译： 集成RF功率放大器20包括片上输入变压器（24）和片上输出变压器（28）。 每个变压器（24,28）由四个螺旋形成。 每个初级绕组（34,42）和每个次级绕组（38,44）包括正和负螺旋，其被布置成使得正电流在正和负螺旋中沿相反的旋转方向旋转。 输入变压器（24）的次级绕组（38）和输出变压器（28）的初级绕组（42）各自具有位于绕组的电和物理中心的中心抽头（48,50）。 正和负放大器（26）耦合在输入变压器（24）的次级绕组和输出变压器（28）的初级绕组之间。 放大器（26）的直流偏置通过中心抽头绕组（38,42）的正和负螺旋从相应的中心抽头（48,50）提供。
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4.发明授权公开(公告)号：US06281778B1
公开(公告)日：2001-08-28
申请号：US09442375
申请日：1999-11-17
IPC分类号： H01F500
CPC分类号： H01F17/0006 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A monolithic inductor (20, 20′) is formed over a silicon or other substrate (22). The inductor (20, 20′) includes at least one coil (62, 78) arranged so that its axis (58) is parallel to the substrate (22). Other inductive features, such as other coils (64, 70, 72) or planar spirals (74, 76) are arranged in series with the coil (62, 78) to guide magnetic flux lines away from the substrate (22). In one embodiment, a common thin film coil core (60) made from a magnetic material is provided for two coils (62, 64). The coil core (60) provides a continuous magnetic material flux path through the two coils (62, 64). In another embodiment, an axis (58) of the coil (78) is located between the plane in which two spirals (74, 76) are located and the substrate (22) to guide magnetic flux lines (82) away from the substrate (22).
摘要翻译： 在硅或其它衬底（22）上形成单片电感器（20,20'）。 电感器（20,20'）包括布置成使得其轴线（58）平行于衬底（22）的至少一个线圈（62,78）。 诸如其它线圈（64,70,72）或平面螺旋（74,76）的其它电感特征与线圈（62,78）串联布置以将磁通线引导离开衬底（22）。 在一个实施例中，为两个线圈（62,64）提供由磁性材料制成的公共薄膜线圈芯（60）。 线圈芯（60）提供穿过两个线圈（62,64）的连续的磁性材料通量路径。 在另一个实施例中，线圈（78）的轴线（58）位于两个螺旋（74,76）所在的平面和衬底（22）之间，以引导磁通线（82）远离衬底（ 22）。
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5.发明授权Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction 失效异质结双极晶体管具有宽带隙，低互扩散基极 - 发射极结
公开(公告)号：US5912481A
公开(公告)日：1999-06-15
申请号：US939487
申请日：1997-09-29
IPC分类号： H01L29/73 , H01L21/331 , H01L29/267 , H01L29/737 , H01L29/70 , H01L29/732
CPC分类号： H01L29/66242 , H01L29/267 , H01L29/7378
摘要： A heterojunction bipolar transistor (20) is provided with a silicon (Si) base region (34) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36) proximate the base region (34) and a distal gallium phosphide emitter layer (40). The GaAs emitter layer (36) is sufficiently thin, preferably less than 200 .ANG., so as to be coherently strained.
摘要翻译： 异质结双极晶体管（20）设置有硅（Si）基区（34），其与具有接近基极区域（GaAs）的薄砷化镓（GaAs）发射极层（36）的多层发射极（38）形成半导体结， 34）和远端磷化镓发射极层（40）。 GaAs发射极层（36）足够薄，优选地小于200，以致相干地变形。
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公开(公告)号：US06545571B2
公开(公告)日：2003-04-08
申请号：US09955378
申请日：2001-09-12
IPC分类号： H03B518
CPC分类号： H01P7/10 , H03B5/1864
摘要： A HE0&ggr;&dgr; mode dielectric resonator (12) includes a cylindrical dielectric disk (32) having top and bottom ends (20, 22) spaced apart by a closed curve wall (24). The dielectric disk (32) has a dielectric constant greater than 40. An axially aligned hole (36) is formed through the disk (32) between the top and bottom ends (20, 22). A conductive wall (34) is formed at the closed curved wall (24) but not the top and bottom ends (20, 22). The hole (36) has a preferred diameter less than 0.2 times the diameter of the disk. A tuning plug (30) is formed from a material having a dielectric constant less than 0.5 times the dielectric constant of the dielectric disk (32) and an unloaded quality factor greater than 2.0 times the unloaded quality factor of the dielectric disk (32). The tuning plug is inserted to a desired depth within the hole (36) of the dielectric disk (32).
摘要翻译： 一个电容模式介质谐振器（12）包括一个圆柱形电介质盘（32），它具有由封闭曲线壁（24）隔开的顶端和底端（20,22）。 电介质盘（32）具有大于40的介电常数。在顶端和底端（20,22）之间通过盘（32）形成轴向对齐的孔（36）。 导电壁（34）形成在封闭的弯曲壁（24）上，而不是顶端和底端（20,22）。 孔（36）具有小于盘直径的0.2倍的优选直径。 调谐塞（30）由介电常数小于电介质盘（32）的介电常数的0.5倍的材料和大于电介质盘（32）的无负载品质因数的2.0倍的无载质量因子的材料形成。 调谐插头插入介质盘（32）的孔（36）内的所需深度。
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7.发明授权Method of forming heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction 失效形成具有宽带隙，低互扩散基极 - 发射极结的异质结双极晶体管的方法公开(公告)号：US06171920B2
公开(公告)日：2001-01-09
申请号：US09267252
申请日：1999-03-12
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/267 , H01L29/7378
摘要： A heterojunction bipolar transistor (20) is provided with a silicon (Si) base region (34) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36) proximate the base region (34) and a distal gallium phosphide emitter layer (40). The GaAs emitter layer (36) is sufficiently thin, preferably less than 200 Å, so as to be coherently strained.
摘要翻译： 异质结双极晶体管（20）设置有硅（Si）基区（34），其与具有接近基极区域（GaAs）的薄砷化镓（GaAs）发射极层（36）的多层发射极（38）形成半导体结， 34）和远端磷化镓发射极层（40）。 GaAs发射极层（36）足够薄，优选小于200，以致相干地变形。
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公开(公告)号：US6008694A
公开(公告)日：1999-12-28
申请号：US113724
申请日：1998-07-10
CPC分类号： H03F1/0288 , H03F3/604 , H03F3/607
摘要： A distributed amplifier (10) configured to amplify an input signal (20) is presented. Within the amplifier (10), a first input phase-shift element (40) shifts the input signal (20) into a first shifted input signal (56). A first active element (18'), coupled to the first input phase-shift element (40), amplifies the first shifted input signal (56) into a first amplified signal (58). A second phase-shift element (42), coupled to the first input phase-shift element (40), shifts the first shifted input signal (56) into a second shifted input signal (62). A second active element (18"), coupled to the second phase-shift element (42), amplifies the second shifted input signal (62) into a second amplified signal (64). A first output phase-shift element (44), coupled to the first active element (18'), shifts the first amplified signal (58) into a first shifted amplified signal (60). A second output phase-shift element (46), coupled to the first output phase-shift element (44) and the second active element (18"), shifts the first shifted amplified signal (60) and the second amplified signal (64) into an output signal (24).
摘要翻译： 呈现配置成放大输入信号（20）的分布式放大器（10）。 在放大器（10）内，第一输入相移元件（40）将输入信号（20）移位到第一移位输入信号（56）中。 耦合到第一输入相移元件（40）的第一有源元件（18'）将第一移位输入信号（56）放大成第一放大信号（58）。 耦合到第一输入相移元件（40）的第二相移元件（42）将第一移位输入信号（56）移位到第二移位输入信号（62）中。 耦合到第二相移元件（42）的第二有源元件（18“）将第二移位输入信号（62）放大成第二放大信号（64）。 耦合到第一有源元件（18'）的第一输出相移元件（44）将第一放大信号（58）移位到第一移位放大信号（60）中。 耦合到第一输出相移元件（44）和第二有源元件（18“）的第二输出相移元件（46）移位第一移位放大信号（60）和第二放大信号（64 ）输入到输出信号（24）中。
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公开(公告)号：US06423990B1
公开(公告)日：2002-07-23
申请号：US09441576
申请日：1999-11-17
IPC分类号： H01L310328
CPC分类号： H01L29/66863 , H01L29/1004 , H01L29/267 , H01L29/66242 , H01L29/7371 , H01L29/7378
摘要： A heterojunction bipolar transistor (20, 60) is provided with a silicon (Si) base region (34, 74) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36, 72) proximate the base region (34, 74) and a distal gallium phosphide (GaP) emitter layer (40, 66). The GaAs emitter layer (36, 72) is sufficiently thin, preferably less than 200 Å, so as to be coherently strained. In one embodiment, the GaP emitter layer includes a doped region (70) which serves as the emitter and a non-doped region (68) on which the intrinsic portion of the transistor (60) is formed.
摘要翻译： 异质结双极晶体管（20,60）设置有与具有薄砷化镓（GaAs）发射极层（36,72）的多层发射极（38）形成半导体结的硅（Si）基区（34,74） ）接近所述基极区（34,74）和远端磷化镓（GaP）发射极层（40,66）。 GaAs发射极层（36,72）足够薄，优选小于200，以使其相干应变。 在一个实施例中，GaP发射极层包括用作发射极的掺杂区域（70）和形成晶体管（60）本征部分的非掺杂区域（68）。
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公开(公告)号：US6104631A
公开(公告)日：2000-08-15
申请号：US991966
申请日：1997-12-17
IPC分类号： G11C11/38 , G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/34
CPC分类号： G11C11/412
摘要： A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (V.sub.f) of the tunnel diode (32) controls the V.sub.gs transfer curve (56) of the load transistor.
摘要翻译： 静态RAM存储单元（30）使用交叉耦合增强模式，N沟道MOS驱动晶体管（36）形成双稳态触发器。 负载电路（34）耦合在驱动晶体管（36）和Vcc的I / O端口（40）之间。 对于每个驱动晶体管（36），负载电路包括耗尽模式N沟道MOS负载晶体管（54）和正向偏置隧道二极管（32）。 负载晶体管（54）的漏极和栅极耦合在隧道二极管（32）的阳极和阴极之间，使得隧道二极管（32）的正向电压（Vf）控制负载的Vgs转移曲线（56） 晶体管。
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