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公开(公告)号：US06301147B1
公开(公告)日：2001-10-09
申请号：US09520081
申请日：2000-03-08
IPC分类号： G11C1100
CPC分类号： H01L27/11 , G11C11/38 , G11C11/412 , H01L27/1104
摘要： A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (Vf) of the tunnel diode (32) controls the Vgs transfer curve (56) of the load transistor. The tunnel diode (32) may be formed at a junction between a mono-crystalline silicon layer (88) at a region (98, 100) which also serves as a source or drain of a transistor (36, 54) and a poly-crystalline silicon layer (106). The poly-crystalline silicon layer (106) also serves as a non-metallic, conductive interconnection (55) to save space.
摘要翻译： 静态RAM存储单元（30）使用交叉耦合增强模式，N沟道MOS驱动晶体管（36）形成双稳态触发器。 负载电路（34）耦合在驱动晶体管（36）和Vcc的I / O端口（40）之间。 对于每个驱动晶体管（36），负载电路包括耗尽模式N沟道MOS负载晶体管（54）和正向偏置隧道二极管（32）。 负载晶体管（54）的漏极和栅极耦合在隧道二极管（32）的阳极和阴极之间，使得隧道二极管（32）的正向电压（Vf）控制负载的Vgs转移曲线（56） 晶体管。 隧道二极管（32）可以形成在也用作晶体管（36,54）的源极或漏极的区域（98,100）处的单晶硅层（88）之间的结处， 晶体硅层（106）。 多晶硅层（106）还用作非金属导电互连（55）以节省空间。
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2.发明授权公开(公告)号：US06281778B1
公开(公告)日：2001-08-28
申请号：US09442375
申请日：1999-11-17
IPC分类号： H01F500
CPC分类号： H01F17/0006 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A monolithic inductor (20, 20′) is formed over a silicon or other substrate (22). The inductor (20, 20′) includes at least one coil (62, 78) arranged so that its axis (58) is parallel to the substrate (22). Other inductive features, such as other coils (64, 70, 72) or planar spirals (74, 76) are arranged in series with the coil (62, 78) to guide magnetic flux lines away from the substrate (22). In one embodiment, a common thin film coil core (60) made from a magnetic material is provided for two coils (62, 64). The coil core (60) provides a continuous magnetic material flux path through the two coils (62, 64). In another embodiment, an axis (58) of the coil (78) is located between the plane in which two spirals (74, 76) are located and the substrate (22) to guide magnetic flux lines (82) away from the substrate (22).
摘要翻译： 在硅或其它衬底（22）上形成单片电感器（20,20'）。 电感器（20,20'）包括布置成使得其轴线（58）平行于衬底（22）的至少一个线圈（62,78）。 诸如其它线圈（64,70,72）或平面螺旋（74,76）的其它电感特征与线圈（62,78）串联布置以将磁通线引导离开衬底（22）。 在一个实施例中，为两个线圈（62,64）提供由磁性材料制成的公共薄膜线圈芯（60）。 线圈芯（60）提供穿过两个线圈（62,64）的连续的磁性材料通量路径。 在另一个实施例中，线圈（78）的轴线（58）位于两个螺旋（74,76）所在的平面和衬底（22）之间，以引导磁通线（82）远离衬底（ 22）。
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3.发明授权Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction 失效异质结双极晶体管具有宽带隙，低互扩散基极 - 发射极结
公开(公告)号：US5912481A
公开(公告)日：1999-06-15
申请号：US939487
申请日：1997-09-29
IPC分类号： H01L29/73 , H01L21/331 , H01L29/267 , H01L29/737 , H01L29/70 , H01L29/732
CPC分类号： H01L29/66242 , H01L29/267 , H01L29/7378
摘要： A heterojunction bipolar transistor (20) is provided with a silicon (Si) base region (34) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36) proximate the base region (34) and a distal gallium phosphide emitter layer (40). The GaAs emitter layer (36) is sufficiently thin, preferably less than 200 .ANG., so as to be coherently strained.
摘要翻译： 异质结双极晶体管（20）设置有硅（Si）基区（34），其与具有接近基极区域（GaAs）的薄砷化镓（GaAs）发射极层（36）的多层发射极（38）形成半导体结， 34）和远端磷化镓发射极层（40）。 GaAs发射极层（36）足够薄，优选地小于200，以致相干地变形。
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4.发明授权Method of forming heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction 失效形成具有宽带隙，低互扩散基极 - 发射极结的异质结双极晶体管的方法公开(公告)号：US06171920B2
公开(公告)日：2001-01-09
申请号：US09267252
申请日：1999-03-12
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/267 , H01L29/7378
摘要： A heterojunction bipolar transistor (20) is provided with a silicon (Si) base region (34) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36) proximate the base region (34) and a distal gallium phosphide emitter layer (40). The GaAs emitter layer (36) is sufficiently thin, preferably less than 200 Å, so as to be coherently strained.
摘要翻译： 异质结双极晶体管（20）设置有硅（Si）基区（34），其与具有接近基极区域（GaAs）的薄砷化镓（GaAs）发射极层（36）的多层发射极（38）形成半导体结， 34）和远端磷化镓发射极层（40）。 GaAs发射极层（36）足够薄，优选小于200，以致相干地变形。
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公开(公告)号：US06423990B1
公开(公告)日：2002-07-23
申请号：US09441576
申请日：1999-11-17
IPC分类号： H01L310328
CPC分类号： H01L29/66863 , H01L29/1004 , H01L29/267 , H01L29/66242 , H01L29/7371 , H01L29/7378
摘要： A heterojunction bipolar transistor (20, 60) is provided with a silicon (Si) base region (34, 74) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36, 72) proximate the base region (34, 74) and a distal gallium phosphide (GaP) emitter layer (40, 66). The GaAs emitter layer (36, 72) is sufficiently thin, preferably less than 200 Å, so as to be coherently strained. In one embodiment, the GaP emitter layer includes a doped region (70) which serves as the emitter and a non-doped region (68) on which the intrinsic portion of the transistor (60) is formed.
摘要翻译： 异质结双极晶体管（20,60）设置有与具有薄砷化镓（GaAs）发射极层（36,72）的多层发射极（38）形成半导体结的硅（Si）基区（34,74） ）接近所述基极区（34,74）和远端磷化镓（GaP）发射极层（40,66）。 GaAs发射极层（36,72）足够薄，优选小于200，以使其相干应变。 在一个实施例中，GaP发射极层包括用作发射极的掺杂区域（70）和形成晶体管（60）本征部分的非掺杂区域（68）。
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公开(公告)号：US6104631A
公开(公告)日：2000-08-15
申请号：US991966
申请日：1997-12-17
IPC分类号： G11C11/38 , G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/34
CPC分类号： G11C11/412
摘要： A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (V.sub.f) of the tunnel diode (32) controls the V.sub.gs transfer curve (56) of the load transistor.
摘要翻译： 静态RAM存储单元（30）使用交叉耦合增强模式，N沟道MOS驱动晶体管（36）形成双稳态触发器。 负载电路（34）耦合在驱动晶体管（36）和Vcc的I / O端口（40）之间。 对于每个驱动晶体管（36），负载电路包括耗尽模式N沟道MOS负载晶体管（54）和正向偏置隧道二极管（32）。 负载晶体管（54）的漏极和栅极耦合在隧道二极管（32）的阳极和阴极之间，使得隧道二极管（32）的正向电压（Vf）控制负载的Vgs转移曲线（56） 晶体管。
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7.发明授权
公开(公告)号：US6013939A
公开(公告)日：2000-01-11
申请号：US962377
申请日：1997-10-31
IPC分类号： H01L21/822 , H01F17/00 , H01L23/522 , H01L27/04 , H01L27/08 , H01L29/00 , G01R1/04
CPC分类号： H01F17/0006 , H01L23/5227 , H01L27/08 , H01L2924/0002
摘要： A monolithic inductor (20, 20') is formed over a silicon or other substrate (22). The inductor (20, 20') includes at least one coil (62, 78) arranged so that its axis (58) is parallel to the substrate (22). Other inductive features, such as other coils (64, 70, 72) or planar spirals (74, 76) are arranged in series with the coil (62, 78) to guide magnetic flux lines away from the substrate (22). In one embodiment, a common thin film coil core (60) made from a magnetic material is provided for two coils (62, 64). The coil core (60) provides a continuous magnetic material flux path through the two coils (62, 64). In another embodiment, an axis (58) of the coil (78) is located between the plane in which two spirals (74, 76) are located and the substrate (22) to guide magnetic flux lines (82) away from the substrate (22).
摘要翻译： 在硅或其它衬底（22）上形成单片电感器（20,20'）。 电感器（20,20'）包括布置成使得其轴线（58）平行于衬底（22）的至少一个线圈（62,78）。 诸如其它线圈（64,70,72）或平面螺旋（74,76）的其它电感特征与线圈（62,78）串联布置以将磁通线引导离开衬底（22）。 在一个实施例中，为两个线圈（62,64）提供由磁性材料制成的公共薄膜线圈芯（60）。 线圈芯（60）提供穿过两个线圈（62,64）的连续的磁性材料通量路径。 在另一个实施例中，线圈（78）的轴线（58）位于两个螺旋（74,76）所在的平面和衬底（22）之间，以引导磁通线（82）远离衬底（ 22）。
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8.发明授权公开(公告)号：US06885853B2
公开(公告)日：2005-04-26
申请号：US09833438
申请日：2001-04-11
申请人： Kazim Sevens , Majid M. Hashemi , Ismail H. Ozguc
发明人： Kazim Sevens , Majid M. Hashemi , Ismail H. Ozguc
CPC分类号： H03J3/08
摘要： A receiver (22) includes an IF filter (44) and a nearby process-variant circuit (80) formed on a common semiconductor substrate (24). The actual center frequency of the IF filter (44) is determined by resistors (70, 74) and capacitors (72, 76) exhibiting imprecise values and is unlikely to equal a nominal center frequency. The process-variant circuit (80) includes a test resistor (102) and test capacitor (104) formed using the same resistor-forming and capacitor-forming processes used to form the IF filter resistors (70, 74) and capacitors (72, 76). In response a test signal (88) from the process-variant circuit (80) and a reference signal (84) from a process-invariant circuit (82), a tuning parameter for a tunable local oscillator (90) is determined so that a local oscillation signal (94) will exhibit a frequency which, when mixed with an RF signal (38) yields an IF signal (42) at the actual center frequency of the IF filter (44).
摘要翻译： 接收器（22）包括形成在公共半导体衬底（24）上的IF滤波器（44）和附近的过程变量电路（80）。 中频滤波器（44）的实际中心频率由电阻（70,74）和显示不精确值的电容器（72,76）确定，并且不太可能等于标称中心频率。 过程变量电路（80）包括使用与形成IF滤波电阻（70,74）和电容器（72,74）相同的电阻器形成和电容器形成工艺形成的测试电阻器（102）和测试电容器（104） 76）。 响应于来自过程变量电路（80）的测试信号（88）和来自过程不变电路（82）的参考信号（84），确定可调谐本地振荡器（90）的调谐参数，使得 本地振荡信号（94）将呈现频率，当与RF信号（38）混合时，IF滤波器（44）的实际中心频率产生IF信号（42）。
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9.发明授权Method of fabricating self-aligned FET structure having a high temperature stable T-shaped Schottky gate contact 失效制造具有高温稳定的T形肖特基栅极接触的自对准FET结构的方法
公开(公告)号：US5550065A
公开(公告)日：1996-08-27
申请号：US344911
申请日：1994-11-25
IPC分类号： H01L21/285 , H01L21/338 , H01L29/417 , H01L29/423 , H01L29/47 , H01L21/265
CPC分类号： H01L29/66878 , H01L21/28587 , H01L29/41775 , H01L29/42316 , H01L29/475 , Y10S148/003 , Y10S148/10 , Y10S148/131 , Y10S148/14
摘要： A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN "T-shaped" Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the "T-shaped" gate, with source and drain ohmic contacts also self-aligned with respect to the gate.
摘要翻译： 制造具有GaAs或InP的半绝缘衬底的自对准FET的方法，其具有通过在邻近表面的衬底中通过分子束外延或金属有机气相外延掺杂表面或外延生长的沟道而形成的导电沟道。 在衬底表面形成高温稳定的LaB6 / TiWN“T型”肖特基栅极接触，用于源极和漏极欧姆区注入到与衬底相邻的衬底中并与“T形”栅极自对准 源极和漏极欧姆触点也相对于栅极自对准。
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公开(公告)号：US5514606A
公开(公告)日：1996-05-07
申请号：US270275
申请日：1994-07-05
申请人： Majid M. Hashemi , Saied N. Tehrani
发明人： Majid M. Hashemi , Saied N. Tehrani
IPC分类号： H01L21/338 , H01L23/31 , H01L29/812
CPC分类号： H01L29/66863 , H01L23/3171 , H01L29/812 , H01L29/8128 , H01L2924/0002 , H01L2924/13063
摘要： A method of fabricating high breakdown voltage MESFETs forming a conduction channel in a GaAs substrate adjacent the surface, forming high temperature stable source and drain ohmic contacts and a Schottky gate contact on the surface of the substrate in overlying relationship to the channel and in spaced relationship, and depositing a layer of low temperature GaAs passivation material over the substrate surface and the source, drain and gate contacts. Openings are then etched in the passivation material for contacting the source, drain and gate contacts.
摘要翻译： 制造在击穿表面附近的GaAs衬底中形成导电沟道的高耐压MESFET的方法，在衬底的表面上形成高温稳定的源极和漏极欧姆接触和肖特基门接触，并以间隔的关系 ，并在衬底表面和源极，漏极和栅极触点上沉积一层低温GaAs钝化材料。 然后在钝化材料中蚀刻开口以接触源极，漏极和栅极触点。
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