公开(公告)号：US20040169530A1

公开(公告)日：2004-09-02

申请号：US10672061

申请日：2003-09-26

申请人： Engim, Inc.

发明人： Gabriele Manganaro

IPC分类号： H03F003/45

CPC分类号： H03F3/45085 ,  H03F2203/45508 ,  H03F2203/45544 ,  H03F2203/45548 ,  H03F2203/45596 ,  H03F2203/45622 ,  H03F2203/45702

摘要： A base bias circuit generates a bias voltage for a bipolar transistor. The base bias circuit includes a current mirror circuit which tracks current through a current source which drives emitter current through the bipolar transistor. A primary biasing bipolar transistor and a secondary bipolar transistor have a null which tracks the null of the bipolar transistor. The primary biasing bipolar transistor receives current from the current source through a current mirror circuit to develop the bias voltage. A bias resistor coupled between the bias voltage and the base of the primary biasing bipolar transistor tracks resistance variations in the base resistor. The secondary biasing transistor tracks changes in base current to the bipolar transistor and supplies additional current to the primary biasing transistor to compensate for changes in null.

摘要翻译： 基极偏置电路产生用于双极晶体管的偏置电压。 基极偏置电路包括电流镜电路，其跟踪通过电流源的电流，该电流源驱动通过双极晶体管的发射极电流。 主偏置双极晶体管和次级双极晶体管具有跟踪双极晶体管的β的β。 主偏置双极晶体管通过电流镜电路从电流源接收电流以产生偏置电压。 耦合在偏置电压和初级偏置双极晶体管的基极之间的偏置电阻器跟踪基极电阻器中的电阻变化。 次级偏置晶体管跟踪到双极晶体管的基极电流的变化，并向初级偏置晶体管提供附加电流以补偿β的变化。

公开(公告)号：US20040161055A1

公开(公告)日：2004-08-19

申请号：US10731417

申请日：2003-12-09

申请人： Engim, Inc.

发明人： Amit Sinha

IPC分类号： H04L027/14

CPC分类号： H04L27/227 ,  G06F7/4818 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0067

摘要： The invention relates to using a shift-and-add technique with a group of pre-calculated angles, such as the Coordinated Rotation Digital Computer (CORDIC) algorithm, in a hardware efficient digital carrier offset compensation loop. The implementation uses the shift-and-add technique for an efficient arctangent structure calculating phase offset errors. The implementation optionally uses the shift-and-add technique as a Numerically Controlled Oscillator (NCO) to track and compensate for a phase shift.

摘要翻译： 本发明涉及在硬件高效数字载波偏移补偿环路中使用具有一组预先计算的角度的移位和加法技术，例如协调旋转数字计算机（CORDIC）算法。 该实现使用移位和加法技术来计算相位偏移误差的有效反正切结构。 该实现可选地使用移位和加法技术作为数控振荡器（NCO）来跟踪和补偿相移。

公开(公告)号：US20040121749A1

公开(公告)日：2004-06-24

申请号：US10703198

申请日：2003-11-06

申请人： Engim, Inc.

发明人： Jian Cui ,  David Shoemaker ,  John Trotter

IPC分类号： H04B017/00 ,  H04B001/10 ,  H04Q007/24 ,  H04M003/00

CPC分类号： H04W72/085 ,  H04W24/10 ,  H04W84/12

摘要： A Channel Association method and apparatus for a wireless Network increases data throughput by intelligently associating clients to channels. Data rates are assigned to channels and clients with a similar data rate are associated to the same channel. The association is based on the client's distance from a host, the received power of each client and the performance of the client at the host.

摘要翻译： 用于无线网络的信道关联方法和装置通过智能地将客户端关联到信道来增加数据吞吐量。 数据速率被分配给信道，并且具有与相同信道相关联的类似数据速率的客户端。 该协会基于客户与主机的距离，每个客户端的接收功率以及客户端在主机上的性能。

公开(公告)号：US20040174810A1

公开(公告)日：2004-09-09

申请号：US10731730

申请日：2003-12-09

申请人： Engim, Inc.

发明人： Maneesh Soni ,  Kanu Chadha ,  Manish Bhardwaj

IPC分类号： H04J011/00 ,  H04Q007/24

CPC分类号： H04L25/05

摘要： Upon a triggering event, a delay chain shifts data out at a higher rate than incoming packets and a processor controls bypassing circuitry to reduce the latency of hardware implementations of, for example, 802.11a OFDM receivers, with long delay chains. The signal processing algorithms used to recover symbol timing need a large number of samples stored in a delay chain, often consisting of pipelined registers. Such a delay chain introduces a large lag between the time samples have been acquired by the data converters and the time they are processed. This delay makes it difficult for higher level network layer implementations to meet the deadlines of 802.11a WLAN protocol. The proposed scheme implements dynamic reduction in the depth of the delay chain once timing recovery has been performed. A multi-step scheme achieves exponential reduction in the number of elements in the delay chain in every step.

摘要翻译： 在触发事件时，延迟链以比输入分组更高的速率移出数据，并且处理器控制旁路电路以减少具有长延迟链的例如802.11a OFDM接收机的硬件实现的等待时间。 用于恢复符号定时的信号处理算法需要存储在延迟链中的大量采样，通常由流水线寄存器组成。 这样的延迟链在由数据转换器获取的时间样本和它们被处理的时间之间引入了大的滞后。 这种延迟使得较高级别的网络层实现难以满足802.11a WLAN协议的最后期限。 一旦定时恢复被执行，所提出的方案实现延迟链的深度的动态降低。 多步骤方案实现了每个步骤中延迟链中元素数量的指数减少。

公开(公告)号：US20040170237A1

公开(公告)日：2004-09-02

申请号：US10712800

申请日：2003-11-13

申请人： Engim, Inc.

发明人： Kanu Chadha ,  Maneesh Soni ,  Manish Bhardwaj

IPC分类号： H04L027/06

CPC分类号： H04L27/2675 ,  H04L27/261 ,  H04L27/2663 ,  H04L27/2665 ,  H04L27/2676

摘要： Using a combination of auto-correlation and cross-correlation techniques provides a symbol timing recovery in a Wireless Local Area Network (WLAN) environment that is extremely robust to wireless channel impairments such as noise, multi-path and carrier frequency offset. An auto-correlator provides an estimate for a symbol boundary, and a cross-correlator is subsequently used to more precisely identify the symbol boundary. Peak processing of the cross-correlation results provides further refinement in symbol boundary detection. In receiving a packet conforming to the IEEE 802.11a standard, the method requires a minimum of only three short symbols of the 802.11a short preamble to determine timing, and guarantees timing lock within the duration of the 802.11a short preamble. This method and system can be easily applied to any other preamble based system such as 802.11g and High Performance Radio LAN/2 (HIPERLAN/2).

摘要翻译： 使用自相关和互相关技术的组合在无线局域网（WLAN）环境中提供对诸如噪声，多径和载波频率偏移之类的无线信道损伤非常鲁棒的符号定时恢复。 自相关器提供符号边界的估计，随后使用互相关器更精确地识别符号边界。 互相关结果的峰值处理提供了符号边界检测的进一步细化。 在接收符合IEEE 802.11a标准的数据包时，该方法只需要802.11a短前导码中只有三个短符号，以确定定时，并保证802.11a短前导码持续时间内的定时锁定。 该方法和系统可以容易地应用于诸如802.11g和高性能无线LAN / 2（HIPERLAN / 2）的任何其它基于前导码的系统。

公开(公告)号：US20040152418A1

公开(公告)日：2004-08-05

申请号：US10703192

申请日：2003-11-06

申请人： Engim, Inc.

发明人： Amit Sinha ,  Manish Bhardwaj ,  Kanu Chadha

IPC分类号： H04B001/02

CPC分类号： H04L27/0002 ,  H04W88/00

摘要： A unified digital front end filtering circuit is described for IEEE 802.11g protocol compliant systems. The front end uses polyphase rate conversion filters cascaded with channel extraction and pulse shaping filters to accommodate the different sampling rate requirements for orthogonal frequency division multiplexing (OFDM) and direct sequence spread spectrum (DSSS) modulation, which have to be supported simultaneously, without using separate analog front ends.

摘要翻译： 针对符合IEEE 802.11g协议的系统描述了统一的数字前端滤波电路。 前端使用与通道提取和脉冲整形滤波器级联的多相速率转换滤波器，以适应正交频分复用（OFDM）和直接序列扩频（DSSS）调制的不同采样率要求，必须同时支持，而不使用 单独的模拟前端。

公开(公告)号：US20040268207A1

公开(公告)日：2004-12-30

申请号：US10851697

申请日：2004-05-21

申请人： Engim, Inc.

发明人： Sudhir K. Sharma

IPC分类号： G11C029/00 ,  H03M013/00

CPC分类号： H03M13/6502 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/107 ,  H03M13/271 ,  H03M13/2792 ,  H03M13/2796 ,  H03M13/6527

摘要： A rate-converting, low-latency, low power interleaver architecture is implemented using block read-write methods. The memory architecture is such that it allows multiple input bits to be written into memory simultaneously. In some embodiments, the number of simultaneous bits written into memory corresponds to an error encoding rate, such that an encoder and interleaver can operate within the same clock domain, regardless of the code rate. The memory architecture also allows an entire row of interleaved data to be read out in one clock cycle.

摘要翻译： 使用块读写方法实现了速率转换，低延迟，低功耗交织器架构。 存储器结构使得它允许多个输入位被同时写入存储器。 在一些实施例中，写入存储器的同时位数对应于错误编码率，使得编码器和交织器可以在相同的时钟域内操作，而不管码率如何。 存储器架构还允许在一个时钟周期中读出整行交错数据。

公开(公告)号：US20040156309A1

公开(公告)日：2004-08-12

申请号：US10713562

申请日：2003-11-14

申请人： Engim, Inc.

发明人： Kanu Chadha ,  Manish Bhardwaj

IPC分类号： H04J011/00

CPC分类号： H04L27/2662 ,  H04L27/266 ,  H04L27/2675

摘要： The invention relates to a novel methodology and apparatus for clock-offset compensation and common-phase offset correction in Frequency Division Multiplixing based wireless local area network (WLAN) environment, such as an Orthogonal Frequency Division Multiplexing (OFDM) environment. A curve fit, such as a threshold-based, least mean squares (LMS) fit of phase of the pilot sub-carriers in each OFDM symbol is used to estimate and counteract the rotation of the data sub-carriers due to residual frequency offset, low frequency phase noise, and clock offset. The invention is particularly well suited to wireless channels with multipath where pilots typically undergo frequency-selective fading. The thresholding LMS is implemented in a hardware-efficient manner, offering cost advantages over a weighted-LMS alternative. Additionally, the invention uses a unique phase-feedback architecture to eliminate the effects of phase wrapping, and avoid the need to refine channel estimates during packet reception.

摘要翻译： 本发明涉及一种用于基于频分复用的无线局域网（WLAN）环境中的时分偏移补偿和公共相位偏移校正的新颖的方法和装置，例如正交频分复用（OFDM）环境。 使用曲线拟合，例如每个OFDM符号中的导频子载波的相位的基于阈值的最小均方（LMS）拟合，以估计和抵消由于残余频率偏移导致的数据子载波的旋转， 低频相位噪声和时钟偏移。 本发明特别适用于具有多径的无线信道，其中导频通常经历频率选择性衰落。 阈值LMS以硬件有效的方式实现，提供了超过加权LMS替代方案的成本优势。 此外，本发明使用独特的相位反馈架构来消除相位缠绕的影响，并且避免在分组接收期间精细化信道估计的需要。

公开(公告)号：US20040117764A1

公开(公告)日：2004-06-17

申请号：US10703207

申请日：2003-11-06

申请人： Engim, Inc.

发明人： Amit Sinha ,  Tom McKinney

IPC分类号： G06F009/44

CPC分类号： H03H17/0685 ,  H03H17/0223 ,  H03H17/0225 ,  H03H17/0227 ,  H03H17/0294 ,  H03H2218/085

摘要： A programmable hardware architecture and design methodology for the implementation of a sample rate conversion engine is presented. The conversion engine supports scalable filter taps and can be tuned to a range of interpolation and decimation requirements. The conversion engine can be used effectively in wideband systems to efficiently extract and process digital sequences with protocol specific sampling rate requirements. The conversion engine can also be used as a hardware accelerator for software defined radios and communication systems that require adaptive sampling rates.

摘要翻译： 提出了一种用于实现采样率转换引擎的可编程硬件架构和设计方法。 转换引擎支持可扩展的滤波器抽头，可以调整到一系列插值和抽取要求。 转换引擎可以有效地用于宽带系统，以有效提取和处理具有协议特定采样率要求的数字序列。 转换引擎还可以用作需要自适应采样率的软件定义无线电和通信系统的硬件加速器。

公开(公告)号：US20040008133A1

公开(公告)日：2004-01-15

申请号：US10462086

申请日：2003-06-13

申请人： Engim, Inc.

发明人： Gabriele Manganaro

IPC分类号： H03M001/66

CPC分类号： H03M1/804

摘要： A digital-to-analog converter (DAC) with high linearity includes a switched capacitor amplifier removably coupled to a capacitor array. The result of the conversion by the capacitor array is sampled by the switched capacitor amplifier directly from the capacitor in the most significant cell in the array. The switched capacitor amplifier includes a memory capacitor and a feedback capacitor. The memory capacitor provides the initial output voltage corresponding to the result of the conversion when coupled to the capacitor array and stores the output voltage while the feedback capacitor is reset.

摘要翻译： 具有高线性度的数模转换器（DAC）包括可拆卸地耦合到电容器阵列的开关电容放大器。 电容器阵列的转换结果由开关电容放大器直接从阵列中最重要的单元中的电容器采样。 开关电容放大器包括存储电容器和反馈电容器。 当耦合到电容器阵列时，存储电容器提供对应于转换结果的初始输出电压，并且在反馈电容器被复位时存储输出电压。