公开(公告)号：US09479051B2

公开(公告)日：2016-10-25

申请号：US13340746

申请日：2011-12-30

申请人： Chien-Chung Tseng ,  Eric Soenen ,  Alan Roth ,  Justin Shi

发明人： Chien-Chung Tseng ,  Eric Soenen ,  Alan Roth ,  Justin Shi

IPC分类号： G05F1/577 ,  H02M3/158 ,  H02M1/00

CPC分类号： H02M3/158 ,  H02M2001/009

摘要： A DC to DC converter includes a switching circuit and a controller. The switching circuit includes an inductor coupled to first and second voltage supply nodes and to a plurality of output loads. The controller is configured to monitor a current through the inductor and to selectively couple the inductor to each of the plurality of output loads such that at least one of the following criteria is met: 1) an average current through the inductor is minimized for the particular output loads coupled to the switching circuit, or 2) minimize a number of times the switching circuit is switched during a charging period for the particular output loads coupled to the switching circuit.

摘要翻译： DC-DC转换器包括开关电路和控制器。 开关电路包括耦合到第一和第二电压供应节点和耦合到多个输出负载的电感器。 控制器被配置为监测通过电感器的电流并且选择性地将电感器耦合到多个输出负载中的每一个，使得满足以下标准中的至少一个：1）通过电感器的平均电流对于特定的 耦合到开关电路的输出负载，或2）在耦合到开关电路的特定输出负载的充电周期期间最小化开关电路切换的次数。

公开(公告)号：US08971004B2

公开(公告)日：2015-03-03

申请号：US13546303

申请日：2012-07-11

申请人： Alan Roth ,  Eric Soenen

发明人： Alan Roth ,  Eric Soenen

IPC分类号： H02H5/04

CPC分类号： G05B11/01 ,  G01K7/16 ,  G01K15/005 ,  G05B15/02 ,  H03M3/344 ,  H03M3/458

摘要： A high accuracy on-chip thermal sensor includes an integrated circuit and sensing elements. The thermal sensor finds application in various mobile and battery powered devices and includes a processor that analyzes a measured temperature signal and decides if the thermal sensor operates in low or high power operational mode, or if the device's CPU is to be reset. A method utilizing the thermal sensor includes making comparisons to two threshold temperatures and operating at low power mode below the first threshold temperature, high power mode between the two threshold temperatures and causing reset if the second threshold temperature is exceeded. Low power operational mode includes a lower clock frequency, lower bias current and lower power consumption. Higher power operational mode is used when the upper threshold temperature is being approached and includes a higher data sampling frequency and more accurate temperature control and uses higher power.

摘要翻译： 高精度片上热传感器包括集成电路和感测元件。 热传感器可用于各种移动和电池供电的设备，并包括一个处理器，用于分析测量的温度信号，并决定热传感器是在低功耗还是高功率运行模式下运行，或者设备的CPU是否被复位。 利用热传感器的方法包括比较两个阈值温度并在低于第一阈值温度的低功率模式下工作，在两个阈值温度之间的高功率模式，并且如果超过第二阈值温度则引起复位。 低功耗操作模式包括较低的时钟频率，较低的偏置电流和较低的功耗。 当接近上限阈值时使用更高功率的工作模式，并且包括更高的数据采样频率和更准确的温度控制，并且使用更高的功率。

公开(公告)号：US20130272545A1

公开(公告)日：2013-10-17

申请号：US13446047

申请日：2012-04-13

申请人： Martin KINYUA ,  Eric SOENEN ,  Ruopeng WANG

发明人： Martin KINYUA ,  Eric SOENEN ,  Ruopeng WANG

IPC分类号： H03F99/00 ,  H03F3/217

CPC分类号： H03F3/217 ,  H03F1/0205 ,  H03F1/26 ,  H03F3/2173

摘要： A pulse width modulation (PWM) amplifier includes a first amplifier stage, a second amplifier stage, and a gain module. The first amplifier stage is configured to amplify an analog input signal in the analog and digital domains using a first pulse width modulation (PWM) generator, to provide a first stage output for coupling to a load. The gain module is configured to amplify a quantization error of the first PWM generator by a predetermined gain. The second amplifier stage is configured to spectrally shape and attenuate the amplified quantization error of the first PWM generator using a second PWM generator, to provide a second stage output for coupling to the load.

公开(公告)号：US08324955B2

公开(公告)日：2012-12-04

申请号：US13051343

申请日：2011-03-18

申请人： Alan Roth ,  Ying-Chih Hsu ,  Justin Shi ,  Eric Soenen

发明人： Alan Roth ,  Ying-Chih Hsu ,  Justin Shi ,  Eric Soenen

IPC分类号： H03L5/00

CPC分类号： H03K19/018507 ,  H03K3/037

摘要： A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V1 and a second voltage V2. The output from the invert is capacitively coupled to an input of a latch circuit via a capacitor. The capacitor has a first terminal connected to the output terminal of the first inverter, and further has a second terminal. The level shifter has a resistor connected to a third voltage V3 and to the capacitor for tying the input to the latch circuit to a desired voltage. The latch circuit is configured to operate at a potential difference between a fourth voltage V4 and a fifth voltage V5. The latch has an input node connected to the resistor and the capacitor, and further has an output node connected to an output node of the level shifter.

摘要翻译： 电平移位器接收输入电压信号并产生输出电压信号。 电平移位器包括第一反相器，其被配置为在第一电压V1和第二电压V2之间的电位差下工作。 反相器的输出通过电容电容耦合到锁存电路的输入端。 电容器具有连接到第一反相器的输出端子的第一端子，并且还具有第二端子。 电平移位器具有连接到第三电压V3的电阻器和用于将输入端连接到锁存电路的电容器以达到期望的电压。 闩锁电路被配置为在第四电压V4和第五电压V5之间的电位差下工作。 锁存器具有连接到电阻器和电容器的输入节点，并且还具有连接到电平移位器的输出节点的输出节点。

公开(公告)号：US08547267B2

公开(公告)日：2013-10-01

申请号：US13481990

申请日：2012-05-29

申请人： Alan Roth ,  Eric Soenen ,  Chia Liang Tai

发明人： Alan Roth ,  Eric Soenen ,  Chia Liang Tai

IPC分类号： H03M3/00

CPC分类号： G05B11/01 ,  G01K7/16 ,  G01K15/005 ,  G05B15/02 ,  H03M3/344 ,  H03M3/458

摘要： A hysteretic digital filter includes a first multi-bit flip-flop having an input for receiving a series of multi-bit sigma-delta ADC codes, a clock input for receiving a clock signal and an output; a second multi-bit flip-flop having an input coupled to the output of the first multi-bit flip-flop, an output for providing an output code of the digital filter, and an input for receiving a latch control signal, the second multi-bit flip-flop latching its input to its output under control of the latch control signal; and a control circuit. The control circuit is configured to selectively provide the latch control signal to trigger latching by the second multi-bit flip-flop dependent on a running comparison of the output code of the digital filter and the value of individual ones of the multi-bit sigma-delta ADC codes from the series of multi-bit sigma-delta ADC codes.

摘要翻译： 迟滞数字滤波器包括具有用于接收一系列多比特Σ-ΔADC码的输入的第一多位触发器，用于接收时钟信号和输出的时钟输入; 具有耦合到第一多位触发器的输出的输入的第二多位触发器，用于提供数字滤波器的输出码的输出和用于接收锁存控制信号的输入，第二多位触发器 位触发器在锁存控制信号的控制下将其输入锁存到其输出端; 和控制电路。 控制电路被配置为根据数字滤波器的输出代码的运行比较和多比特Σ-位触发器的各个值的选择性地提供锁存控制信号以触发第二多位触发器的锁存， 来自多位Σ-ΔADC代码的Delta ADC代码。

公开(公告)号：US20130135131A1

公开(公告)日：2013-05-30

申请号：US13481990

申请日：2012-05-29

申请人： Chia Liang Tai ,  Alan ROTH ,  Eric SOENEN

发明人： Chia Liang Tai ,  Alan ROTH ,  Eric SOENEN

IPC分类号： H03M3/02

CPC分类号： G05B11/01 ,  G01K7/16 ,  G01K15/005 ,  G05B15/02 ,  H03M3/344 ,  H03M3/458

摘要： A hysteretic digital filter includes a first multi-bit flip-flop having an input for receiving a series of multi-bit sigma-delta ADC codes, a clock input for receiving a clock signal and an output; a second multi-bit flip-flop having an input coupled to the output of the first multi-bit flip-flop, an output for providing an output code of the digital filter, and an input for receiving a latch control signal, the second multi-bit flip-flop latching its input to its output under control of the latch control signal; and a control circuit. The control circuit is configured to selectively provide the latch control signal to trigger latching by the second multi-bit flip-flop dependent on a running comparison of the output code of the digital filter and the value of individual ones of the multi-bit sigma-delta ADC codes from the series of multi-bit sigma-delta ADC codes.

摘要翻译： 迟滞数字滤波器包括具有用于接收一系列多比特Σ-ΔADC码的输入的第一多位触发器，用于接收时钟信号和输出的时钟输入; 具有耦合到第一多位触发器的输出的输入的第二多位触发器，用于提供数字滤波器的输出码的输出和用于接收锁存控制信号的输入，第二多位触发器 位触发器在锁存控制信号的控制下将其输入锁存到其输出端; 和控制电路。 控制电路被配置为根据数字滤波器的输出代码的运行比较和多比特Σ-位触发器的各个值的选择性地提供锁存控制信号以触发第二多位触发器的锁存， 来自多位Σ-ΔADC代码的Delta ADC代码。

公开(公告)号：US20130009795A1

公开(公告)日：2013-01-10

申请号：US13619034

申请日：2012-09-14

申请人： Eric SOENEN ,  Alan ROTH ,  Martin KINYUA ,  Justin SHI ,  Justin GAITHER

发明人： Eric SOENEN ,  Alan ROTH ,  Martin KINYUA ,  Justin SHI ,  Justin GAITHER

IPC分类号： H03M3/02 ,  H03M1/12

CPC分类号： H03M3/344 ,  H03H17/00 ,  H03M3/00 ,  H03M3/464

摘要： A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.

摘要翻译： 包括模数转换器（ADC）的电路。 ADC配置为接收模拟反馈信号和模拟输入信号并产生数字输出。 电路还包括噪声整形器。 噪声整形器被配置为截断数字输出并产生具有比数字输出低的位数的噪声整形器输出，并且形成在截断期间产生的量化噪声。 电路还包括脉宽调制数模转换器（PWM DAC）。 PWM DAC被配置为处理噪声整形器输出的截断数字输出并产生PWM DAC输出。

公开(公告)号：US08305246B2

公开(公告)日：2012-11-06

申请号：US12892487

申请日：2010-09-28

申请人： Martin Kinyua ,  Eric Soenen

发明人： Martin Kinyua ,  Eric Soenen

IPC分类号： H03M3/02

CPC分类号： H03M3/344 ,  H03F3/217 ,  H03M3/506

摘要： A class D amplifier is configured to accept a digital input signal wherein the control loop of the class D amplifier employs a hybrid filter merged with the front-end of a sigma-delta ADC converter. The term hybrid refers to the filter using both digital and analog components in which the digital delay elements serve as shift registers while the filter coefficients are analog. The filter converts the digital PDM data into a step-wise sinusoidal signal. The sigma-delta ADC receiving a feedback signal subtracts the step-wise sinusoidal signal from the continuous sinusoidal signal and converts the result to a digital PDM signal, without decimation, which passes through a digital filter, a PWM generator, and a pre-driver, to provide power to the load.

摘要翻译： D类放大器被配置为接受数字输入信号，其中D类放大器的控制环采用与Σ-ΔADC转换器的前端并入的混合滤波器。 术语混合是指使用数字和模拟组件的滤波器，其中数字延迟元件用作移位寄存器，而滤波器系数是模拟的。 滤波器将数字PDM数据转换成逐级正弦信号。 接收反馈信号的Σ-ΔADC从连续正弦信号中减去逐级正弦信号，并将结果转换成数字PDM信号，而不抽抽，其通过数字滤波器，PWM发生器和预驱动器 ，为负载提供电力。

公开(公告)号：US20120133345A1

公开(公告)日：2012-05-31

申请号：US12956630

申请日：2010-11-30

申请人： Chia-Liang TAI ,  Alan ROTH ,  Eric SOENEN

发明人： Chia-Liang TAI ,  Alan ROTH ,  Eric SOENEN

IPC分类号： G05F1/10

CPC分类号： G05F1/575 ,  G01R1/203 ,  G05F1/00 ,  G05F1/10 ,  G05F1/40 ,  G05F1/56 ,  H02M3/156

摘要： A hysteretic power converter includes a comparator, a calibration circuit, and an output node having an output voltage. The calibration circuit is configured to supply a calibrated voltage to the comparator. The comparator controls the output voltage based on the calibrated voltage and a feedback voltage representing at least a portion of the output voltage.

摘要翻译： 迟滞功率转换器包括比较器，校准电路和具有输出电压的输出节点。 校准电路被配置为向比较器提供经校准的电压。 比较器基于校准的电压和表示输出电压的至少一部分的反馈电压来控制输出电压。

公开(公告)号：US20120038340A1

公开(公告)日：2012-02-16

申请号：US12856918

申请日：2010-08-16

申请人： Justin SHI ,  Alan ROTH ,  Justin GAITHER ,  Eric SOENEN

发明人： Justin SHI ,  Alan ROTH ,  Justin GAITHER ,  Eric SOENEN

IPC分类号： G05F1/10

CPC分类号： H02M3/04 ,  H02M3/156 ,  H02M2001/0032 ,  Y02B70/16

摘要： Some embodiments regard a method of controlling a regulator having an input voltage and an output voltage, comprising: turning on a first driver; determining a duration ratio having a first time period over the first time period and a second time period; the first time period and the second time period indicating a duration when the first driver and a second driver is on, respectively; generating a second voltage level for the reference voltage based on the duration ratio and a ripple voltage that is a difference between a high threshold voltage and a low threshold voltage; turning off the first driver and turning on the second driver based on a relationship between the second voltage level and a voltage level of the output voltage; turning off the second driver when a current flowing through a node of the output voltage reaches a pre-determined level; and generating a change in the first time period based on the duration ratio and a voltage difference between a peak of the output voltage and the high threshold voltage.

摘要翻译： 一些实施例涉及一种控制具有输入电压和输出电压的调节器的方法，包括：打开第一驱动器; 确定在所述第一时间段和第二时间段内具有第一时间段的持续时间比; 所述第一时间段和所述第二时间段分别指示所述第一驾驶员和所述第二驾驶员开启时的持续时间; 基于持续时间比产生用于参考电压的第二电压电平，以及纹波电压，其是高阈值电压和低阈值电压之间的差; 基于第二电压电平和输出电压的电压电平之间的关系，关闭第一驱动器并接通第二驱动器; 当流过输出电压的节点的电流达到预定电平时，关闭第二驱动器; 以及基于所述持续时间比和所述输出电压的峰值与所述高阈值电压之间的电压差来产生所述第一时间段的变化。