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公开(公告)号：US11539329B2
公开(公告)日：2022-12-27
申请号：US17319433
申请日：2021-05-13
Applicant: Eridan Communications, Inc.
Inventor： Waclaw Godycki
Abstract: A wideband envelope modulator comprises a direct current (DC)-to-DC switching converter connected in series with a linear amplitude modulator (LAM). The DC-DC switching converter includes a pulse-width modulator that generates a PWM signal with modulated pulse widths representing a time varying magnitude of an input envelope signal or a pulse-density modulator that generates a PDM signal with a modulated pulse density representing the time varying magnitude of the input envelope signal, a field-effect transistor (FET) driver stage that generates a differential PWM or PDM drive signal, a high-power output switching stage that is driven by the PWM or PDM drive signal, and an output energy storage network including a low-pass filter (LPF) of order greater than two that filters a switching voltage produced at an output switching node of the high-power output switching stage.
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公开(公告)号：US10084448B2
公开(公告)日：2018-09-25
申请号：US15176487
申请日：2016-06-08
Applicant: Eridan Communications, Inc.
Inventor： Waclaw Godycki
IPC: H03K17/687 , H03K5/08 , H03K17/74 , H03K17/691 , H01L29/778 , H01L29/20 , H03F3/217 , H03F3/193 , H02M3/158
CPC classification number: H03K17/6871 , H01L29/2003 , H01L29/778 , H02M3/158 , H03F3/193 , H03F3/2171 , H03F3/2173 , H03F2200/171 , H03F2200/331 , H03F2200/351 , H03F2200/451 , H03K5/08 , H03K17/063 , H03K17/691 , H03K17/74
Abstract: A driver interface for a switch-based circuit includes an AC coupling capacitor, a first diode or a first series of diodes, and a second diode or a second series of diodes connected in series with the first diode or first series of diodes but with an opposing polarity. The AC coupling capacitor removes a DC voltage from an input bi-level drive signal that does not have the appropriate high and low drive levels needed to switch a FET in the switch-based circuit between fully ON and fully OFF states. The first diode or first series of diodes and the second diode or second series of diodes clamp the resulting AC-coupled drive signal to produce an output bi-level drive signal having the high and low drive levels needed to switch the FET between fully ON and fully OFF states. The driver interface maintains the high and low drive levels of the output bi-level drive signal irrespective of any changes made to the duty cycle or pulse density of the input bi-level drive signal.
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公开(公告)号：US11038466B2
公开(公告)日：2021-06-15
申请号：US16544172
申请日：2019-08-19
Applicant: Eridan Communications, Inc.
Inventor： Waclaw Godycki
Abstract: A wideband envelope modulator comprises a direct current (DC)-to-DC switching converter connected in series with a linear amplitude modulator (LAM). The DC-DC switching converter includes a pulse-width modulator that generates a PWM signal with modulated pulse widths representing a time varying magnitude of an input envelope signal or a pulse-density modulator that generates a PDM signal with a modulated pulse density representing the time varying magnitude of the input envelope signal, a field-effect transistor (FET) driver stage that generates a PWM or PDM drive signal, a high-power output switching stage that is driven by the PWM or PDM drive signal, and an output energy storage network including a low-pass filter (LPF) of order greater than two that filters a switching voltage produced at an output switching node of the high-power output switching stage.
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公开(公告)号：US20210058035A1
公开(公告)日：2021-02-25
申请号：US16544172
申请日：2019-08-19
Applicant: Eridan Communications, Inc.
Inventor： Waclaw Godycki
Abstract: A wideband envelope modulator comprises a direct current (DC)-to-DC switching converter connected in series with a linear amplitude modulator (LAM). The DC-DC switching converter includes a pulse-width modulator that generates a PWM signal with modulated pulse widths representing a time varying magnitude of an input envelope signal or a pulse-density modulator that generates a PDM signal with a modulated pulse density representing the time varying magnitude of the input envelope signal, a field-effect transistor (FET) driver stage that generates a PWM or PDM drive signal, a high-power output switching stage that is driven by the PWM or PDM drive signal, and an output energy storage network including a low-pass filter (LPF) of order greater than two that filters a switching voltage produced at an output switching node of the high-power output switching stage.
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Patent Agency Ranking
公开(公告)号：US10778111B1
公开(公告)日：2020-09-15
申请号：US16570948
申请日：2019-09-13
Applicant: Eridan Communications, Inc.
Inventor： Waclaw Godycki
IPC: H02M5/293
Abstract: A current regulating apparatus capable of regulating an electrical current with a high level of precision and over a wide range of voltages includes a first depletion mode field-effect transistor (FET), a second depletion mode FET, and a fixed resistor. The second depletion mode FET and fixed resistor are connected in series and across the gate-source terminals of the first depletion mode FET. The first depletion mode FET operates as an adjustable current source while the second depletion mode FET is controlled to operate as a voltage controlled resistor. The magnitude of current regulated by the current regulating apparatus is determined based on both the resistance of the fixed resistor and a current-setting control voltage applied to the gate of the second depletion mode FET. Various precision values of regulated current can be realized by simply changing the current-setting control voltage.
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公开(公告)号：US20210265952A1
公开(公告)日：2021-08-26
申请号：US17319433
申请日：2021-05-13
Applicant: Eridan Communications, Inc.
Inventor： Waclaw Godycki
Abstract: A wideband envelope modulator comprises a direct current (DC)-to-DC switching converter connected in series with a linear amplitude modulator (LAM). The DC-DC switching converter includes a pulse-width modulator that generates a PWM signal with modulated pulse widths representing a time varying magnitude of an input envelope signal or a pulse-density modulator that generates a PDM signal with a modulated pulse density representing the time varying magnitude of the input envelope signal, a field-effect transistor (FET) driver stage that generates a differential PWM or PDM drive signal, a high-power output switching stage that is driven by the PWM or PDM drive signal, and an output energy storage network including a low-pass filter (LPF) of order greater than two that filters a switching voltage produced at an output switching node of the high-power output switching stage.
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7.发明授权公开(公告)号：US10707822B1
公开(公告)日：2020-07-07
申请号：US16563847
申请日：2019-09-07
Applicant: Eridan Communications, Inc.
Inventor： Waclaw Godycki
Abstract: A dynamic power supply (DPS) for polar modulation transmitters and envelope tracking (ET) transmitters includes a direct current (DC)-DC converter, a linear amplitude modulator (LAM) connected in series with the DC-DC converter, and a controller that dynamically controls both the switching of the DC-DC converter and the magnitude of the LAM's reference voltage, depending on time-varying changes in an input envelope voltage Venv. The DC-DC converter includes a high-power buck switching stage and an output energy storage network having a third-order or higher low-pass filter (LPF). The third-order or higher LPF filters out switching noise and ripple from the switching voltage produced by the high-power buck switching stage, and in one embodiment of the invention is augmented by a damping network that eliminates undesirable ringing at the power supply input of the LAM, thereby increasing efficiency and DPS conversion precision.
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公开(公告)号：US20180262192A1
公开(公告)日：2018-09-13
申请号：US15976055
申请日：2018-05-10
Applicant: Eridan Communications, Inc.
Inventor： Waclaw Godycki
IPC: H03K17/687 , H03K5/08 , H02M3/158 , H03F3/217 , H01L29/20 , H01L29/778 , H03K17/691 , H03K17/74 , H03F3/193
CPC classification number: H03K17/6871 , H01L29/2003 , H01L29/778 , H02M3/158 , H03F3/193 , H03F3/2171 , H03F3/2173 , H03F2200/171 , H03F2200/331 , H03F2200/351 , H03F2200/451 , H03K5/08 , H03K17/063 , H03K17/691 , H03K17/74
Abstract: A driver interface for a switch-based circuit includes an AC coupling capacitor, a first diode or a first series of diodes, and a second diode or a second series of diodes connected in series with the first diode or first series of diodes but with an opposing polarity. The AC coupling capacitor removes a DC voltage from an input bi-level drive signal that does not have the appropriate high and low drive levels needed to switch a FET in the switch-based circuit between fully ON and fully OFF states. The first diode or first series of diodes and the second diode or second series of diodes clamp the resulting AC-coupled drive signal to produce an output bi-level drive signal having the high and low drive levels needed to switch the FET between fully ON and fully OFF states. The driver interface maintains the high and low drive levels of the output bi-level drive signal irrespective of any changes made to the duty cycle or pulse density of the input bi-level drive signal.
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公开(公告)号：US20170359060A1
公开(公告)日：2017-12-14
申请号：US15176487
申请日：2016-06-08
Applicant: Eridan Communications, Inc.
Inventor： Waclaw Godycki
IPC: H03K17/687 , H02M3/158 , H03K17/691 , H03K5/08 , H03F3/193 , H01L29/778 , H01L29/20 , H03K17/74 , H03F3/217
CPC classification number: H03K17/6871 , H01L29/2003 , H01L29/778 , H02M3/158 , H03F3/193 , H03F3/2171 , H03F3/2173 , H03F2200/171 , H03F2200/331 , H03F2200/351 , H03F2200/451 , H03K5/08 , H03K17/063 , H03K17/691 , H03K17/74
Abstract: A driver interface for a switch-based circuit includes an AC coupling capacitor, a first diode or a first series of diodes, and a second diode or a second series of diodes connected in series with the first diode or first series of diodes but with an opposing polarity. The AC coupling capacitor removes a DC voltage from an input bi-level drive signal that does not have the appropriate high and low drive levels needed to switch a FET in the switch-based circuit between fully ON and fully OFF states. The first diode or first series of diodes and the second diode or second series of diodes clamp the resulting AC-coupled drive signal to produce an output bi-level drive signal having the high and low drive levels needed to switch the FET between fully ON and fully OFF states. The driver interface maintains the high and low drive levels of the output bi-level drive signal irrespective of any changes made to the duty cycle or pulse density of the input bi-level drive signal.
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