利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.013 秒)

    NOR-type mask ROM having dual sense current paths
    1.
    发明授权
    NOR-type mask ROM having dual sense current paths 失效
    NOR型掩模ROM具有双重感测电流路径

    公开(公告)号：US5923606A

    公开(公告)日：1999-07-13

    申请号：US954905

    申请日：1997-10-21

    申请人： Woon-Kyung Lee ,  Eui-Do Kim

    发明人： Woon-Kyung Lee ,  Eui-Do Kim

    IPC分类号： H01L21/8246 ,  H01L27/112 ,  G11C13/00

    CPC分类号： H01L27/112

    摘要： A NOR-type mask ROM reduces the resistance ratio of buried diffusion layers and improves the drive capacity of bank selection transistors by utilizing sub-bit line selection transistors located near the center of a memory cell array. The sub-bit line selection transistors are connected to a pair of sub-bank selection lines that divide the memory cell array into symmetric upper and lower portions. The bank selection transistors couple alternate sub-bit lines to main bit lines at both ends of the sub-bit lines, thereby forming a dual current path between the main bit lines and the memory cells coupled to the sub-bit lines.

    摘要翻译： NOR型掩模ROM通过利用位于存储单元阵列中心附近的子位线选择晶体管来降低掩埋扩散层的电阻比，并且提高了存储体选择晶体管的驱动能力。 子位线选择晶体管连接到将存储单元阵列分成对称的上部和下部的一对子组选择线。 存储体选择晶体管将副位线耦合到子位线两端的主位线，从而在主位线和耦合到子位线的存储单元之间形成双电流路径。

    Non-volatile memory device having multi-bit cell structure and a method of programming same
    3.
    发明授权
    Non-volatile memory device having multi-bit cell structure and a method of programming same 失效
    具有多位单元结构的非易失性存储器件及其编程方法

    公开(公告)号：US6122188A

    公开(公告)日：2000-09-19

    申请号：US219024

    申请日：1998-12-23

    申请人： Eui-Do Kim ,  Woon-Kyung Lee ,  Jeong-Hyouk Choi

    发明人： Eui-Do Kim ,  Woon-Kyung Lee ,  Jeong-Hyouk Choi

    IPC分类号： H01L27/112 ,  G11C11/56 ,  H01L21/8246 ,  G11C17/00

    CPC分类号： G11C11/5692 ,  H01L27/1126

    摘要： There is provided a non-volatile memory device having a multi-bit cell structure. In the non-volatile memory device, a memory cell array includes a plurality of cells of a first conductivity type which has different threshold voltages and are arranged in a matrix on a semiconductor substrate. A bulk region of a second conductivity type opposite to the first conductivity underlies the memory cell array and receives a predetermined back bias voltage when a cell is driven. The threshold voltage difference between states can be sufficiently widened because a state having a high bulk concentration is highly susceptible to a body effect. Therefore, reduction of masks leads to process simplicity, reduced turnaround time, and improved process margin.

    摘要翻译： 提供了具有多位单元结构的非易失性存储器件。 在非易失性存储器件中，存储单元阵列包括具有不同阈值电压并且以矩阵形式布置在半导体衬底上的第一导电类型的多个单元。 与第一导电性相反的第二导电类型的体区域位于存储单元阵列的底部，并且当单元被驱动时接收预定的反向偏置电压。 由于具有高体积浓度的状态对身体效应非常敏感，所以状态之间的阈值电压差可以被充分地加宽。 因此，减少面罩会导致过程简单，缩短周转时间，并改善工艺余量。

    Mask ROM fabrication method
    4.
    发明授权
    Mask ROM fabrication method 失效
    掩模ROM制作方法

    公开(公告)号：US07008848B2

    公开(公告)日：2006-03-07

    申请号：US10713117

    申请日：2003-11-17

    申请人： Woon-kyung Lee ,  He-jueng Lee ,  Eui-do Kim

    发明人： Woon-kyung Lee ,  He-jueng Lee ,  Eui-do Kim

    IPC分类号： H01L21/8236

    CPC分类号： H01L27/112 ,  H01L27/1126

    摘要： A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask ROM fabrication process, a gate insulation layer is formed over a semiconductor substrate, and parallel conductive layer patterns are formed on the gate insulation layer. These conductive layer patterns are separated from each other by a first predetermined interval and extend in the same direction. Ion implantation is then carried out using the conductive layer patterns as a mask to form buried impurity diffusion regions near the semiconductor substrate between the conductive layer patterns. A conductive layer for use in forming word lines is then formed over the entire surface of the resultant structure, and both the conductive layer and the conductive layer patterns are etched so as to form word lines and pad conductive layers. The word lines are formed to be parallel to each other, are separated from each other by a second predetermined interval, and extend in a direction perpendicular to the buried impurity diffusion regions. The pad conductive layers, which form ohmic contacts with the word lines, are formed in an island shape channel regions. These channel regions are defined as the areas between the buried impurity diffusion regions that are overlapped by the word lines.

    摘要翻译： 提供了一种掩模只读存储器（ROM）及其制造方法。 该掩模ROM和相关方法能够减少掩埋的杂质扩散区的间距。 在掩模ROM制造工艺中，在半导体衬底上形成栅极绝缘层，并且在栅极绝缘层上形成平行的导电层图案。 这些导电层图案彼此分开第一预定间隔并沿相同的方向延伸。 然后使用导电层图案作为掩模进行离子注入，以在导电层图案之间的半导体衬底附近形成掩埋的杂质扩散区。 然后在所得结构的整个表面上形成用于形成字线的导电层，并且蚀刻导电层和导电层图案，以形成字线和焊盘导电层。 字线形成为彼此平行，彼此分开第二预定间隔，并且在垂直于埋置的杂质扩散区域的方向上延伸。 与字线形成欧姆接触的焊盘导电层形成为岛状沟道区域。 这些沟道区域被定义为由字线重叠的掩埋杂质扩散区域之间的区域。

    Nonvolatile memory device
    5.
    发明授权
    Nonvolatile memory device 有权
    非易失性存储器件

    公开(公告)号：US06346733B1

    公开(公告)日：2002-02-12

    申请号：US09345581

    申请日：1999-06-30

    申请人： Woon-Kyung Lee ,  Youn-Ho Lee ,  Eui-Do Kim

    发明人： Woon-Kyung Lee ,  Youn-Ho Lee ,  Eui-Do Kim

    IPC分类号： H01L2976

    CPC分类号： H01L27/1126 ,  G11C17/126 ,  H01L27/112 ,  Y10S438/926

    摘要： A nonvolatile memory device is provided in which cell uniformity is significantly improved. The device includes a plurality of burial N+ diffusion layers extending over the surface of a semiconductor substrate. The plurality of burial N+ diffusion layers are the source/drains of cell transistors and the sub bit-lines of the memory cell array. The device additionally includes a plurality of word lines formed over the semiconductor substrate with gate dielectrics interposed therebetween. The plurality of word lines extend perpendicularly to the burial N+ diffusion layers. A plurality of select lines extend parallel to the word lines and selectively transfer external electrical signals via main bit-lines to the sub bit-lines. The main bit-lines extend parallel to said sub bit-lines. Finally, dummy lines extend parallel to the word lines in the spaces between the select lines and the adjacent word lines.

    摘要翻译： 提供了一种非易失性存储器件，其中电池均匀性显着提高。 该装置包括在半导体衬底的表面上延伸的多个埋入N +扩散层。 多个埋置N +扩散层是单元晶体管的源极/漏极和存储单元阵列的子位线。 该器件还包括形成在半导体衬底上的多个字线，其间插入栅极电介质。 多个字线垂直于埋藏的N +扩散层延伸。 多个选择线平行于字线延伸，并且经由主位线选择性地将外部电信号传送到子位线。 主位线平行于所述子位线延伸。 最后，虚拟线平行于选择线和相邻字线之间的空格中的字线延伸。