摘要:
A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.
摘要:
A voltage generating circuit is provided, including a voltage output terminal, a ground terminal, a capacitor, a selector, a first switch, and a second switch. The capacitor is connected between a pump signal and the output of the selector. The selector is controlled by a first control signal and used to select the voltage source or the voltage output terminal to connect the capacitor. The first switch is controlled by a second control signal, and the second switch is controlled by a third control signal. When the first switch is turn-on, the voltage output terminal is connected to the ground terminal. When the second switch is turn-on, the voltage output terminal is connected to the voltage source.
摘要:
A voltage generating circuit is provided, including a voltage output terminal, a ground terminal, a capacitor, a selector, a first switch, and a second switch. The capacitor is connected between a pump signal and the output of the selector. The selector is controlled by a first control signal and used to select the voltage source or the voltage output terminal to connect the capacitor. The first switch is controlled by a second control signal, and the second switch is controlled by a third control signal. When the first switch is turn-on, the voltage output terminal is connected to the ground terminal. When the second switch is turn-on, the voltage output terminal is connected to the voltage source.
摘要:
Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells. The read method comprises the steps of: (d) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by a first verify signal and a second verify signal, and (e) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by the first verify signal and a third verify signal. A page buffer is also disclosed to perform the methods for programming and reading a multi-level-cell NAND flash memory device.
摘要:
A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
摘要:
A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
摘要:
A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.
摘要:
Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells. The read method comprises the steps of: (d) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by a first verify signal and a second verify signal, and (e) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by the first verify signal and a third verify signal. A page buffer is also disclosed to perform the methods for programming and reading a multi-level-cell NAND flash memory device.