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1.发明授权Analog-signal to square-wave-signal reshaping system with offset compensation 失效具有偏移补偿的模拟信号到方波信号整形系统
公开(公告)号：US6031404A
公开(公告)日：2000-02-29
申请号：US994073
申请日：1997-12-19
申请人： Gerhard Roither , Gunther Hackl , Uwe Fischer
发明人： Gerhard Roither , Gunther Hackl , Uwe Fischer
摘要： An analog-signal to square-wave-signal reshaping system for threshold-dependent reshaping of an analog input signal to a square wave signal; comprising an offset-inflicted reshaping circuit having a signal input adapted to be fed with the analog input signal, a reference input adapted to be fed with a reference voltage determining the reshaping threshold, and a signal output from which the square wave signal is available; an offset storage circuit connected to the signal input of the reshaping circuit and adapted to store a charging voltage corresponding to the offset voltage of the reshaping circuit, with this charging voltage being adapted to be superimposed on the analog input signal for offset compensation; a controllable switch circuit which in a first switching state takes no influence on the reshaping function of the reshaping circuit and, for the purpose of offset compensation, in a second switching state interrupts the reshaping operation of reshaping circuit and effects charging of the offset storage circuit to the charging voltage corresponding to the respective offset voltage; a detector circuit by means of which a detection signal can be generated at least approximately at those times at which the analog input signal passes a predetermined detection threshold; a delay circuit by means of which the detection signal can be delayed by a predetermined delay period; and a switch control circuit, by means of which, upon occurrence of the delayed detection signal, the switch circuit can be driven to the second switching state for a predetermined window time duration; with the window time duration lying between the adjacent edges of the square wave signal.
摘要翻译： 模拟信号到方波信号整形系统，用于将模拟输入信号阈值相关重新整形为方波信号; 包括具有适于馈送模拟输入信号的信号输入的偏移造成的重新成形电路，适于馈送用于确定重新定形阈值的参考电压的参考输入以及方波信号可用的信号输出; 偏移存储电路，连接到整形电路的信号输入端，并且适于存储对应于整形电路的偏移电压的充电电压，该充电电压适于叠加在模拟输入信号上用于偏移补偿; 在第一开关状态下的可控开关电路对整形电路的整形功能没有影响，并且为了偏移补偿的目的，在第二开关状态中断重塑电路的重新成形操作并影响偏移存储电路的充电 对应于相应偏移电压的充电电压; 检测器电路，通过该检测器电路可以至少近似地在模拟输入信号通过预定检测阈值的那些时间产生检测信号; 延迟电路，通过该延迟电路可以将检测信号延迟预定的延迟周期; 以及开关控制电路，通过该开关控制电路，在发生延迟的检测信号时，开关电路可以被驱动到第二开关状态达预定的窗口持续时间; 其中窗口持续时间位于方波信号的相邻边缘之间。
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公开(公告)号：US5636249A
公开(公告)日：1997-06-03
申请号：US567880
申请日：1995-12-08
申请人： Gerhard Roither
发明人： Gerhard Roither
CPC分类号： H04H40/18 , H03L7/00 , H04L7/0331 , H04H2201/13
摘要： A method of and an apparatus for phase synchronization of a bit rate clock signal generated in an RDS receiver with a digital RDS signal demodulated on the receiver side, in which both the bit rate clock signal and the RDS signal have the same bit rate. Upon turning on of the RDS receiver and/or switching over of the same to a transmitter receiving frequency different from that received so far, a control signal is generated which, upon occurrence of the next rising edge or, alternatively, of the next falling edge of the RDS signal, effects such a phase angle shift of the bit rate clock signal that the bit rate clock signal, starting from that occurrence, is in phase synchronism with the RDS signal.
摘要翻译： 一种用于在RDS接收机中产生的比特率时钟信号与在接收机侧解调的数字RDS信号相位同步的方法和装置，其中比特率时钟信号和RDS信号都具有相同的比特率。 当RDS接收机接通和/或切换到目前为止接收的发射机接收频率时，产生一个控制信号，该控制信号在下一个上升沿出现时，或者在下一个下降沿 的RDS信号的影响，使比特率时钟信号的这种相位角移动，使得从该事件开始的比特率时钟信号与RDS信号同步。
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公开(公告)号：US5175507A
公开(公告)日：1992-12-29
申请号：US738780
申请日：1991-08-01
申请人： Gerhard Roither
发明人： Gerhard Roither
CPC分类号： H04L25/4904
摘要： A method of demodulating a biphase modulated signal is implemented by first establishing a reference phase angle level. The biphase modulated signal contains a series of bits, each bit having first and second half-bits. The half-bits are represented by opposite phase angle levels. First and second phase angle levels correspond to the first and second half-bits respectively. After the levels associated with first and second half-bits are measured, the two levels are compared. A binary value is assigned to each pair of first and second half-bits based on the relationship of their respective levels. For example, a high phase angle level followed by a low level, can represent the binary value "1", and vice versa.
摘要翻译： 通过首先建立参考相位角来实现解调双相调制信号的方法。 双相调制信号包含一系列位，每个位具有第一和第二半位。 半位由相反的相位角表示。 第一和第二相位角电平分别对应于第一和第二半位。 在测量与第一和第二半位相关联的电平之后，比较两个电平。 基于它们各自的电平的关系，将二进制值分配给每对第一和第二半位。 例如，高相位电平后跟低电平可以表示二进制值“1”，反之亦然。
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公开(公告)号：US6124739A
公开(公告)日：2000-09-26
申请号：US989442
申请日：1997-12-19
申请人： Gerhard Roither , Gunther Hackl , Uwe Fischer
发明人： Gerhard Roither , Gunther Hackl , Uwe Fischer
摘要： A monolithically integrated signal processing circuit comprising a signal series branch connected between a signal input terminal and a signal output terminal; a reference potential terminal; a series capacitor inserted in serial manner in the signal series branch and having a parasitic capacitance acting like a capacitor that is connected between a first electrode of the series capacitor directed towards the signal input terminal and the reference voltage terminal; and a first parallel capacitor connected between the first electrode of the series capacitor and the reference potential terminal; with the first parallel capacitor being constituted at least in part by the parasitic capacitance.
摘要翻译： 一种单片集成信号处理电路，包括连接在信号输入端和信号输出端之间的信号串联分支; 参考电位端子; 串联电容器串联插入信号串联分支中，并具有类似电容器的寄生电容，该寄生电容连接在指向信号输入端子的串联电容器的第一电极和参考电压端子之间; 以及连接在串联电容器的第一电极和参考电位端子之间的第一并联电容器; 其中第一并联电容器至少部分地由寄生电容构成。
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公开(公告)号：US5726992A
公开(公告)日：1998-03-10
申请号：US569781
申请日：1995-12-08
申请人： Gerhard Roither
发明人： Gerhard Roither
CPC分类号： H04H20/02 , H04H40/45 , H04H2201/13 , H04L7/0331
摘要： A method of assessing the quality and/or existence of a biphase-modulated digital RDS signal in a radio signal broadcast by a radio transmitter and received by a radio receiver equipped for RDS, in which a bit rate clock signal is produced on the receiver side whose bit rate is identical to that of the RDS signal, the bits both of the RDS signal and of the bit rate clock signal are each composed of two half bits, and of the two RDS half bits belonging to an RDS bit, one has a positive phase and the other one has a negative phase, and in which, for quality or existence assessment, the number of positive phase signs and the number of negative phase signs are determined which are each contained in the RDS signal during the half bit periods of a predetermined number of n adjacent half bits of the bit rate clock signal, and the RDS signal, depending on whether or not the ratio between the number of positive phase signs ascertained and the number of negative phase signs ascertained corresponds to a predetermined numerical ratio, is rated as being a signal of good quality or as a signal of poor quality, respectively, and in which an odd integer is used for n, which is greater than 2, and preferably is 3.
摘要翻译： 一种在由无线电发射机广播的无线电信号中评估双相调制数字RDS信号的质量和/或存在的方法，所述无线电信号由配备有RDS的无线电接收机接收，其中在接收机侧产生比特率时钟信号 其比特率与RDS信号的比特率相同，RDS信号和比特率时钟信号的比特分别由两个半位组成，并且属于RDS位的两个RDS半位中的一个具有 正相，另一个具有负相位，并且其中，对于质量或存在评估，确定正相位符号的数量和负相位符号的数量，其中每个包含在RDS信号的半位周期期间 比特率时钟信号的预定数量的n个相邻的半位和RDS信号，这取决于确定的正相位符号数与确定的相位符号数之间的比率 分别被认为是质量好的信号或质量差的信号，并且其中使用奇数整数n大于2，优选为3。
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公开(公告)号：US6028469A
公开(公告)日：2000-02-22
申请号：US994791
申请日：1997-12-19
申请人： Gerhard Roither , Gunther Hackl , Uwe Fischer
发明人： Gerhard Roither , Gunther Hackl , Uwe Fischer
摘要： An electric circuit having a switchable feedback branch switchable between a first feedback state, in which the circuit arrangement has a frequency response that is stable with respect to an oscillation tendency, and a second feedback state, in which the circuit arrangement has a frequency response that is unstable with respect to an oscillation tendency. The circuit includes a switchable frequency response compensation circuit which during the first feedback state of the feedback branch can be controlled to an ineffective state and during the second feedback state of the feedback branch can be controlled to an effective state, and in the effective state causes such compensation of the frequency response of the circuit arrangement in the second feedback state that the circuit arrangement in the second feedback state remains stable with respect to an oscillation tendency.
摘要翻译： 一种具有可切换反馈分支的电路，其可在电路装置具有相对于振荡趋势稳定的频率响应的第一反馈状态和第二反馈状态之间切换，其中电路装置具有频率响应， 相对于振荡趋势是不稳定的。 该电路包括可转换频率响应补偿电路，其在反馈支路的第一反馈状态可被控制到无效状态，并且在反馈支路的第二反馈状态期间可被控制到有效状态，并且在有效状态下 在第二反馈状态下电路装置的频率响应的这种补偿，即在第二反馈状态中的电路装置相对于振荡趋势保持稳定。
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7.发明授权
公开(公告)号：US5901188A
公开(公告)日：1999-05-04
申请号：US569849
申请日：1995-12-08
申请人： Gerhard Roither
发明人： Gerhard Roither
CPC分类号： H04L7/033 , H04L7/0331
摘要： A method of phase synchronization of a bit rate clock signal generated on a receiver side with a biphase-modulated digital RDS signal that is demodulated on the receiver side with both signals having the same bit rate. The bits of both the RDS signal and the bit rate clock signal are each composed of two half bits having different digital potential values. The first or the second RDS half bit has a high digital value and the other RDS half bit has a low digital value based on which one of two logic values "1" and "0" is represented by the respective RDS bit. At a first time coinciding with the time of a rising and/or falling edge of a bit of the RDS signal, the digital value of the bit rate clock signal is measured as a first sample value, and at a second time shifted from the first time by a delay time that is shorter than a half bit duration, the digital value of the bit rate clock signal is measured as a second sample value. The phase position of the bit rate clock signal is shifted by a positive or a negative phase angle of a phase angle amount based on whether the two sample values each have a different or an identical digital value.
摘要翻译： 一种在接收机侧产生的比特率时钟信号与在两个信号具有相同比特率的接收机侧解调的双相调制数字RDS信号的相位同步的方法。 RDS信号和比特率时钟信号的位都由具有不同数字电位值的两个半位组成。 第一或第二RDS半位具有高数字值，而另一个RDS半位具有低数字值，基于两个逻辑值“1”和“0”中的哪一个由相应的RDS位表示。 在与RDS信号的位的上升沿和/或下降沿的时间相符的第一时间，比特率时钟信号的数字值被测量为第一采样值，并且在第二时间从第一 时间短于半位持续时间的延迟时间，比特率时钟信号的数字值被测量为第二采样值。 基于两个采样值是否具有不同或相同的数字值，比特率时钟信号的相位位置偏移相位角量的正相位或负相位角。
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