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132 条记录 (耗时 0.021 秒)

    High breakdown voltage III-N depletion mode MOS capacitors
    1.
    发明授权
    High breakdown voltage III-N depletion mode MOS capacitors 有权
    高耐压III-N耗尽型MOS电容

    公开(公告)号：US09064709B2

    公开(公告)日：2015-06-23

    申请号：US13631569

    申请日：2012-09-28

    申请人： Han Wui Then ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

    发明人： Han Wui Then ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

    IPC分类号： H01L27/06 ,  H01L29/93 ,  H01L29/66 ,  H01L29/94 ,  H01L27/08 ,  H01L29/06 ,  H01L29/205 ,  H01L29/04 ,  H01L29/20

    CPC分类号： H01L27/0605 ,  H01L27/0805 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66181 ,  H01L29/93 ,  H01L29/94

    摘要： III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

    摘要翻译： 集成了至少一个具有高击穿电压（BV）的III-N MOS电容器的III-N高压MOS电容器和片上系统（SoC）解决方案，以实现高压和/或高功率电路。 可以实现超过4V的击穿电压，避免了RFIC和/或PMIC中的串联耦合电容的任何需要。 在实施例中，包括其中在低于0V的阈值电压下形成二维电子气（2DEG）的GaN层的耗尽型III-N电容器与IV族晶体管架构单片集成，例如平面和非平面硅CMOS晶体管技术 。 在实施例中，蚀刻硅衬底以提供形成GaN层和III-N势垒层的（111）外延生长表面。 在实施例中，沉积高K电介质层，并且电容器端子触点被制成2DEG并且在电介质层上。

    Power delivery system in which VRM and CPU exchange power consumption measurements
    4.
    发明授权
    Power delivery system in which VRM and CPU exchange power consumption measurements 有权
    供电系统，其中VRM和CPU交换功耗测量

    公开(公告)号：US08694816B2

    公开(公告)日：2014-04-08

    申请号：US12356313

    申请日：2009-01-20

    申请人： Shekhar Borkar ,  Tanay Karnik ,  Peter Hazucha ,  Gerhard Schrom ,  Greg Dermer

    发明人： Shekhar Borkar ,  Tanay Karnik ,  Peter Hazucha ,  Gerhard Schrom ,  Greg Dermer

    IPC分类号： G06F1/26

    CPC分类号： G06F1/28

    摘要： A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.

    摘要翻译： 公开了一种系统。 该系统包括负载，电压调节器电路，耦合到负载电源，耦合到电源以从电源接收一个或多个电压的负载以及耦合在电源和负载之间的数字总线。 数字总线将功耗测量从负载传输到电源，并将功耗测量从电源传输到负载。

    Forming inductor and transformer structures with magnetic materials using damascene processing for integrated circuits
    5.
    发明授权
    Forming inductor and transformer structures with magnetic materials using damascene processing for integrated circuits 有权
    使用集成电路的镶嵌处理形成具有磁性材料的电感器和变压器结构

    公开(公告)号：US08513750B2

    公开(公告)日：2013-08-20

    申请号：US12882529

    申请日：2010-09-15

    申请人： Donald S. Gardner ,  Gerhard Schrom ,  Peter Hazucha ,  Fabrice Paillet ,  Tanay Karnik

    发明人： Donald S. Gardner ,  Gerhard Schrom ,  Peter Hazucha ,  Fabrice Paillet ,  Tanay Karnik

    IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/425 ,  H01L21/469

    CPC分类号： H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

    摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成磁性材料的第一层和设置在第一介电层中的至少一个通孔结构，形成设置在第一磁性层上的第二介电层，形成设置在第二介电层中的至少一个导电结构，形成 设置在所述导电结构上的第三层电介质材料，形成设置在所述第三介电材料层中和所述第二介电材料层中的第二层磁性材料，其中所述磁性材料的第一和第二层与一个 另一个。

    DC-DC CONVERTER SWITCHING TRANSISTOR CURRENT MEASUREMENT TECHNIQUE
    10.
    发明申请
    DC-DC CONVERTER SWITCHING TRANSISTOR CURRENT MEASUREMENT TECHNIQUE 有权
    DC-DC转换器开关晶体管电流测量技术

    公开(公告)号：US20120169425A1

    公开(公告)日：2012-07-05

    申请号：US13417763

    申请日：2012-03-12

    申请人： Gerhard Schrom ,  Peter Hazucha ,  Vivek De ,  Tanay Karnik

    发明人： Gerhard Schrom ,  Peter Hazucha ,  Vivek De ,  Tanay Karnik

    IPC分类号： H03F3/04

    CPC分类号： H02M3/155 ,  G01R19/0092 ,  H02M2001/0009

    摘要： A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.

    摘要翻译： 描述了一种方法，其包括通过开关晶体管导通第一电流。 该方法还包括通过一对晶体管导通第二电流，导体沟道相对于彼此串联耦合并且一起并联耦合在开关晶体管的导电沟道上。 第二电流小于并与第一电流成比例。