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公开(公告)号：US09921592B2
公开(公告)日：2018-03-20
申请号：US14129525
申请日：2013-09-09
摘要： Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.
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公开(公告)号：US09213382B2
公开(公告)日：2015-12-15
申请号：US13612239
申请日：2012-09-12
CPC分类号： G06F1/26 , G05F1/56 , H03K19/00361
摘要： Described is a linear voltage regulator circuit comprising a first voltage regulator comprising a first source follower having a first node to provide a first power supply, and a second node different from the first node; and a second voltage regulator comprising a second source follower having a first node to provide a second power supply, and a second node different from the first node, wherein the second nodes of the first and second voltage regulators are electrically shorted.
摘要翻译： 描述了一种线性稳压器电路，其包括第一电压调节器，其包括具有第一节点以提供第一电源的第一源极跟随器和与第一节点不同的第二节点; 以及第二电压调节器，其包括具有第一节点以提供第二电源的第二源极跟随器，以及不同于所述第一节点的第二节点，其中所述第一和第二稳压器的第二节点被电短路。
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公开(公告)号：US08773233B2
公开(公告)日：2014-07-08
申请号：US13758881
申请日：2013-02-04
申请人： Peter Hazucha , Trang T. Nguyen , Gerhard Schrom , Fabrice Paillet , Donald S. Gardner , Sung T. Moon , Tanay Karnik
发明人： Peter Hazucha , Trang T. Nguyen , Gerhard Schrom , Fabrice Paillet , Donald S. Gardner , Sung T. Moon , Tanay Karnik
IPC分类号： H01F5/00
CPC分类号： H01F27/34 , H01F17/0033 , H01F21/12 , H01F2021/125
摘要： Multiple-inductor embodiments for use in substrates are provided herein.
摘要翻译： 本文提供了用于基板的多电感器实施例。
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4.发明授权Method for manufacturing integrated circuit inductors having slotted magnetic material 有权具有开槽磁性材料的集成电路电感器的制造方法公开(公告)号：US08108984B2
公开(公告)日：2012-02-07
申请号：US12406512
申请日：2009-03-18
IPC分类号： H01F7/06
CPC分类号： H01F17/0006 , H01F10/132 , H01F10/16 , H01F41/34 , H01F2017/0053 , H01F2017/0066 , H01L23/5227 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： Methods of manufacture of integrated circuit inductors having slotted magnetic material will be described. The methods may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.
摘要翻译： 将描述具有开槽磁性材料的集成电路电感器的制造方法。 该方法可以采用电镀或无电镀技术在开槽磁性材料结构内形成一层或多层磁性材料，特别是与绝缘体层相邻的那些磁性材料层。
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公开(公告)号：US20100001826A1
公开(公告)日：2010-01-07
申请号：US12217293
申请日：2008-07-02
CPC分类号： H01F17/0033 , H01F17/0006 , H01F17/02 , H01F27/2804 , H01F41/041 , H01F41/046 , H01F2017/002 , H01F2017/0053 , H01F2017/0066 , Y10T29/4902 , Y10T29/49073 , Y10T29/49126 , Y10T29/49147
摘要： An inductor may be formed from a magnetic film on a package substrate. Conductors coupled either to a die or a voltage converter extend perpendicularly through the film to conductive plates, defining current paths through and across the film.
摘要翻译： 电感器可以由封装衬底上的磁性膜形成。 耦合到管芯或电压转换器的导体垂直延伸穿过膜到导电板，限定穿过膜并穿过膜的电流路径。
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公开(公告)号：US20090267722A1
公开(公告)日：2009-10-29
申请号：US12431882
申请日：2009-04-29
申请人： GERHARD SCHROM , DONALD GARDNER , PETER HAZUCHA , FABRICE PAILLET , TANAY KARNIK
发明人： GERHARD SCHROM , DONALD GARDNER , PETER HAZUCHA , FABRICE PAILLET , TANAY KARNIK
IPC分类号： H01F27/24
CPC分类号： H01F17/0006 , H01F3/00 , H01F27/34 , H01F2017/0066
摘要： An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
摘要翻译： 一种装置包括磁芯，接地节点和一个或多个通孔，以提供磁芯和地电位之间的连接。 磁芯包括第一磁性层和第二磁性层。 另外，该装置可以包括导电图案。 导电图案可以在第一和第二磁性层之间的第三层。 该装置可以包括在使用铁磁芯或屏蔽的电感器，变压器，传输线和其它部件中。 这样的部件可以集成在芯片或芯片上。
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7.发明申请CONTROL OF EDDY CURRENTS IN MAGNETIC VIAS FOR INDUCTORS AND TRANSFORMERS IN INTEGRATED CIRCUITS 失效控制集成电路中电感器和变压器的磁力线的电流公开(公告)号：US20080290980A1
公开(公告)日：2008-11-27
申请号：US12187130
申请日：2008-08-06
CPC分类号： H01F17/0006 , H01F3/12 , H01F10/132 , H01F10/16 , H01F27/324 , H01F41/34 , H01F2027/2819 , H01F2027/348 , H01L23/5226 , H01L23/5227 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , H01L2924/00
摘要： An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
摘要翻译： 一个实施例是磁通孔。 更具体地，实施例是磁通孔，其增加例如集成电感器或变压器的电感，同时减轻其中的涡流，这可能限制电感器或变压器在高频下的操作。
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公开(公告)号：US20080238602A1
公开(公告)日：2008-10-02
申请号：US11694796
申请日：2007-03-30
申请人： GERHARD SCHROM , DONALD GARDNER , PETER HAZUCHA , FABRICE PAILLET , TANAY KARNIK
发明人： GERHARD SCHROM , DONALD GARDNER , PETER HAZUCHA , FABRICE PAILLET , TANAY KARNIK
CPC分类号： H01F17/0006 , H01F17/043 , H01F27/324 , H01F2017/0066 , H01F2027/2819
摘要： An apparatus may include a first magnetic layer, a second magnetic layer, and a conductive pattern. The conductive pattern is at a third layer between the first and second magnetic layers. Moreover, one or more magnetic vias connect the first and second magnetic layers. The magnetic layers and vias may operate as ferromagnetic cores or shields. Further they may be integrated on a chip (on-die magnetics). The apparatus may be included in inductors, transformers, transmission lines, and so forth.
摘要翻译： 装置可以包括第一磁性层，第二磁性层和导电图案。 导电图案位于第一和第二磁性层之间的第三层。 此外，一个或多个磁通孔连接第一和第二磁性层。 磁层和通孔可以作为铁磁芯或屏蔽来操作。 此外，它们可以集成在芯片（片上磁性体）上。 该装置可以包括在电感器，变压器，传输线等中。
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公开(公告)号：US07391640B2
公开(公告)日：2008-06-24
申请号：US11008666
申请日：2004-12-10
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
CPC分类号： G11C11/405 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
摘要翻译： 动态随机存取存储器包括具有浮体晶体管和位线之间的电路的单元。 控制电路的激活以在写入操作期间和在单元未被选择的时间期间在浮体和位线电压之间提供隔离。 增加的隔离可以提高性能，例如，通过减少门到体耦合的需要和位线之间的电压摆幅的大小。
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公开(公告)号：US07386080B2
公开(公告)日：2008-06-10
申请号：US10673218
申请日：2003-09-30
申请人： Fabrice Paillet , Tanay Karnik , Jianping Xu
发明人： Fabrice Paillet , Tanay Karnik , Jianping Xu
IPC分类号： H04L7/00
CPC分类号： H04L7/0079 , H03L7/0812 , H04L7/0008
摘要： A system and method for sampling a data stream generates a number of clock signals having equally spaced phases and then samples a data stream using the clock signals. The clock phases are preferably based on a predetermined fraction of a data rate frequency of the data stream, and sampling is performed based on predetermined combinations of the clock signals. While the system and method is suitable for sampling data transmitted for a wide variety of data rates, the system and method is especially well-suited to sampling at data transmitted at high rates, for example, equal to or greater than 20 Gb/s.
摘要翻译： 用于对数据流进行采样的系统和方法产生具有相等间隔相位的多个时钟信号，然后使用时钟信号对数据流进行采样。 时钟相位优选地基于数据流的数据速率频率的预定分数，并且基于时钟信号的预定组合来执行采样。 虽然系统和方法适合于为各种数据速率传输的数据采样，但是该系统和方法特别适合于以高速率传输的数据进行采样，例如等于或大于20Gb / s。
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