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25 条记录 (耗时 0.021 秒)

    Measuring a characteristic of an integrated circuit
    3.
    发明授权
    Measuring a characteristic of an integrated circuit 有权
    测量集成电路的特性

    公开(公告)号：US06469533B1

    公开(公告)日：2002-10-22

    申请号：US09545922

    申请日：2000-04-10

    申请人： Nasser A. Kurd ,  Keng L. Wong ,  Rachael J. Parker ,  Hung-Piao Ma

    发明人： Nasser A. Kurd ,  Keng L. Wong ,  Rachael J. Parker ,  Hung-Piao Ma

    IPC分类号： G01R3102

    CPC分类号： G01R31/31926 ,  G01R31/31905 ,  G01R31/31915

    摘要： An integrated circuit includes a first circuit, a second circuit, at least one test pad and multiplexing circuitry. The second circuit is coupled to the first circuit and has substantially the same design as the first circuit to emulate an electrical characteristic of the first circuit. The multiplexing circuitry selectively couples the test pad(s) to the second circuit to selectively measure the electrical characteristic.

    摘要翻译： 集成电路包括第一电路，第二电路，至少一个测试焊盘和复用电路。 第二电路耦合到第一电路并且具有与第一电路基本相同的设计，以模拟第一电路的电特性。 多路复用电路选择性地将测试焊盘耦合到第二电路以选择性地测量电特性。

    Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise
    9.
    发明授权
    Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise 失效
    优化时钟分配的方法和装置，以减少电源噪声的影响

    公开(公告)号：US06934872B2

    公开(公告)日：2005-08-23

    申请号：US10021058

    申请日：2001-12-19

    申请人： Keng L. Wong ,  Hung-Piao Ma ,  Tawfik M. Rahal-Arabi ,  Javed Barkatullah ,  Edward A. Burton

    发明人： Keng L. Wong ,  Hung-Piao Ma ,  Tawfik M. Rahal-Arabi ,  Javed Barkatullah ,  Edward A. Burton

    IPC分类号： G06F1/10 ,  G06F1/04 ,  G06F17/50

    CPC分类号： G06F1/10

    摘要： A method and apparatus for optimizing clock distribution in a circuit to reduce the effect of power supply noise. Parameters are determined including: a response curve of a power source for a circuit, a delay sensitivity of a clock net in the circuit to the power source, a delay sensitivity of a data net in the circuit to the power source, a data delay for the data net, and a clock delay for the clock net. The clock delay is adjusted to reduce the effect of power supply noise on the data net. The adjusting is based on the response curve of the power source, the delay sensitivity of the clock net, the delay sensitivity of the data net, the data delay, and the clock delay. The adjusting includes adding a pre-distribution clock delay.

    摘要翻译： 一种用于优化电路中的时钟分布以减少电源噪声的影响的方法和装置。 确定参数，包括：电路的电源的响应曲线，到电源的电路中的时钟网络的延迟灵敏度，电路中的数据网到电源的延迟灵敏度，数据延迟 数据网和时钟网的时钟延迟。 调整时钟延迟以减少电源噪声对数据网的影响。 调整是基于电源的响应曲线，时钟网络的延迟灵敏度，数据网络的延迟灵敏度，数据延迟和时钟延迟。 调整包括添加预分配时钟延迟。

    Multi-stage techniques for accurate shutoff of circuit
    10.
    发明授权
    Multi-stage techniques for accurate shutoff of circuit 有权
    用于电路精确关闭的多级技术

    公开(公告)号：US06265925B1

    公开(公告)日：2001-07-24

    申请号：US09408566

    申请日：1999-09-30

    申请人： Keng L. Wong ,  Hung-Piao Ma

    发明人： Keng L. Wong ,  Hung-Piao Ma

    IPC分类号： H03L500

    CPC分类号： H03K17/693 ,  H03K17/005

    摘要： A multi-stage assembly is disclosed, including a plurality of stages successively arranged, each having a controllable circuit portion and a controlling switching portion coupled thereto. The controlling switching portions have one or more ON/OFF switches which can be MOS transistors, CMOS circuits, etc. A first end of each ON/OFF switch of each controlling switching portion is coupled to a separate node of the controllable circuit portion of that stage and, also, is coupled, respectively, to a second end of a corresponding switch in an adjacent succeeding stage thereby to form selectively actuated one or more strings of series-coupled ON/OFF switches. All switches in an individual string being substantially simultaneously either turned ON or turned OFF. In one such disclosed application, although not limited thereto, the multi-stage assembly features a multi-stage reconfigurable impedance network or, for that matter, a low current/low power biasing network or analog circuit including a cascade arrangement of duplicate circuits in a manner which reduces errors in the output resulting from leakage currents in the turned OFF transistor switches. The number of stages employed, which can be expanded to take into account future scale-downs, also, are based on the level of reduction of subthreshold conduction needed to conform to the error reduction requirements of the circuitry.

    摘要翻译： 公开了一种多级组件，包括连续布置的多个级，每个级具有可控电路部分和与其耦合的控制切换部分。 控制切换部分具有一个或多个可以是MOS晶体管，CMOS电路等的ON / OFF开关。每个控制切换部分的每个ON / OFF开关的第一端耦合到该控制切换部分的可控电路部分的单独节点 并且还分别耦合到相邻后级中相应开关的第二端，从而形成选择性地致动的一个或多个串联耦合的开/关开关串。 单个字符串中的所有开关基本上同时被接通或关闭。 在一个这样公开的应用中，尽管不限于此，多级组件具有多级可重新配置的阻抗网络，或者为此，具有低电流/低功率偏置网络或模拟电路，其包括在 减少由断开晶体管开关中的漏电流导致的输出误差的方法。 可以扩展以考虑到未来缩减的阶段的数量也是基于减少符合电路的误差降低要求所需的亚阈值传导的程度。